Circuit arrangement for the delay adjustment of...

Details Circuit arrangement for the delay adjustment of... Circuit arrangement for the delay adjustment of...

2006-10-24

2006-10-24

Jeanglaude, Jean Bruner (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

With particular solid state devices

C341S155000, C341S079000, C341S118000

Reexamination Certificate

active

07126511

ABSTRACT:
Circuit arrangement (1) for the delay adjustment of analog-to-digital converters (4-1, . . . 4-N,504) operating in a temporally offset manner, having at least two analog-to-digital converters (4-1, . . . 4-N,504) each having a signal path, which receive an analog signal (VI) present at an input (2) of the circuit arrangement (1) and in each case convert it into a digital intermediate signal (Z1, . . . ZN), the analog-to-digital converters (4-1, . . . 4-N,504) in each case being clocked by clock signals (CLK1, . . . CLKN) which have a predetermined time offset with respect to one another; having a logic circuit (7), which interconnects the digital intermediate signals (Z1, . . . ZN) for the purpose of generating a digital output signal (ZD) of the circuit arrangement (1); it being possible to set the bandwidth of the signal paths of the analog-to-digital converters (4-1, . . . 4-N,504) in each case in such a way that a deviation of the clock signal (CLK1, . . . CLKN) from the predetermined time offset for the respective analog-to-digital converter (4-1, . . . 4-N,504) is compensated for by a change in the bandwidth of at least signal path.

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German Office Action dated Oct. 13, 2004.

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