Circuit arrangement for testing parts of a digital time-division

Multiplex communications – Wide area network – Packet switching

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

371 27, 371 204, H04J 314, H04L 1226, H04Q 120

Patent

active

051386089

ABSTRACT:
A receiving circuit for evaluating check words received after traversing a test loop for coincidence with the check word transmitted is utilized in time-division multiplex operation for the sequencing of test implemented in parallel and is reached via a multiplex line on which a defined time slot is allocated to each of the tests.

REFERENCES:
patent: 4592044 (1986-05-01), Ferenc
patent: 4608683 (1986-08-01), Shigaki
patent: 4621354 (1986-11-01), Jones, Jr. et al.
patent: 4821256 (1989-04-01), Schmidt et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Circuit arrangement for testing parts of a digital time-division does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit arrangement for testing parts of a digital time-division, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit arrangement for testing parts of a digital time-division will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-352342

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.