Excavating
Patent
1993-03-05
1995-07-25
Harvey, Jack B.
Excavating
371 216, G11C 1300
Patent
active
054369126
DESCRIPTION:
BRIEF SUMMARY
Circuit arrangement for testing a semiconductor memory by means of parallel tests using various test bit patterns.
BACKGROUND OF THE INVENTION
The invention relates to a circuit arrangement for testing a semiconductor memory by means of parallel tests using various test bit patterns for testing semiconductor memories.
A circuit arrangement of this type is known from the publication with the title "A 60-ns 3.3-V-Only 16-Mbit Dram with Multipurpose Register" by K. Arimoto et al. (Mitsubishi Electric Corporation) in the IEEE Journal of Solid-State Circuits, Vol. 24, No. 5, October 1989 (page 1184 to 1190). This arrangement comprises a circuit arrangement for a parallel line-mode-test (LMT), in which random bit patterns are written into a multi-purpose register (MPR) and into memory cells, the bit patterns read out of these memory cells are compared in comparator circuits with the bit patterns of the MPR and the signals from the comparator output are combined by a wired-OR logic connection, in order to switch the addressed word line over to a back-up word line (redundancy) in the event of a fault.
SUMMARY OF THE INVENTION
The invention is based on the object of specifying a circuit arrangement which allows defective individual memory cells or memory cell n-tuples to be located with minimum expenditure. The locating of defective memory cell n-tuples can be used to redirect memory access demands from defective memory cell n-tuples to fault-free memory cell n-tuples (redundant address).
According to the invention, the object is achieved by a circuit arrangement for testing a semiconductor memory means of parallel tests using various test bit patterns, in which any n-tuples of test bits can be written into at least one n-bit long register. The n-tuple of test bits located in each register can be written via data lines of the semiconductor memory into a multiplicity of memory cell n-tuples having a common word line. The n-tuple of test bits located in each register can be supplied to a multiplicity of comparator circuits. The bit patterns of the memory cell n-tuples having a common word line can be read out via data lines of the semiconductor memory and with which the n-tuples of test bits can be compared in the multiplicity of comparator circuits. The comparator outputs of the multiplicity of comparator circuits are combined by pairs of wired-OR lines to form an address matrix, a pair of wired-OR lines corresponding to an address bit. Each pair of wired-OR lines has a zero-line for the state where the address bit is 0, and a one-line for the state where the address bit is 1. All the wired-OR lines can be switched through to a line which is at a reference potential by means of switching transistors of a first conductance type, in order to discharge them before a respective test. Either the zero-line or the one-line of each pair of wired-OR lines can be switched through, by means of each comparator output, via an associated switching transistor of a second conductance type to a supply voltage. The combination of the switched-through one-lines and zero-lines differs either for all the comparator outputs or for all the n-tuples of comparator outputs. In each case one line of the pairs of wired-OR lines is connected to an address output.
The advantage that can be achieved by means of the invention is that the circuit arrangement designed according to the invention allows better fault locating to be achieved than is the case with the known circuit arrangement, that this arrangement allows individual faults to be distinguished from multiple faults and that, by using a comparator circuit according to the invention, no CMOS level, but merely a few tens of millivolts are required on the data lines connected to the inputs of the comparator circuit.
Preferred embodiments of the circuit arrangement are as follows.
The address matrix is constructed as a fault address matrix, in order to locate faulty individual memory cells. For this purpose a binary code is assigned unambiguously to each comparator output. The supply vol
REFERENCES:
patent: 4384348 (1983-05-01), Nozaki
patent: 5027354 (1991-06-01), Ara et al.
patent: 5060230 (1991-10-01), Arimoto et al.
patent: 5148398 (1992-09-01), Kohno
"A New Array Architecture For Parallel Testing In VLSI Memories", by Y. Matsuda et al, Proceedings of the International Test Conference, Aug. 1989, pp. 322-326.
"Parallel Testing Technology For VLSI Memories" by J. Inoue et al, Proceedings of the International Test COnference, Sep. 1987, pp. 1066-1071.
"Parallel Testing for Pattern Sensitive Faults in Semiconductor Random Access Memories", by P. Mazumder et al, IEEE Transactions on Computers, vol. 38, No. 3, Mar. 1989, pp. 394-407.
"A 60-ns 3.3 V-Only 16-Mbit DRAM with Multipurpose Register", by K. Arimoto et al, IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1184-1190.
Harvey Jack B.
Seto Jeffrey K.
Siemens Aktiengesellschaft
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