Circuit arrangement for testing a digital circuit

Details Circuit arrangement for testing a digital circuit Circuit arrangement for testing a digital circuit

1984-07-12

1987-02-03

Fleming, Michael R.

Excavating

371 20, G06F 304

Patent

active

046413065

ABSTRACT:
Circuit arrangement for dynamic real time testing of a synchronous digital circuit having a clock pulse input, a stimulus input and a circuit node at which a digital test signal is produced after a time delay of .tau. seconds relative to the time of receipt of a signal at the stimulus input. The arrangement includes a clock pulse generator for generating clock pulses; a transmitter device connected to the clock pulse generator and including a counter for counting the clock pulses and a digital signal generator for generating a reproducible digital stimulus signal having a length corresponding to a predetermined count of the counter. The transmitter device is connected for coupling a number of clock pulses corresponding to the predetermined count of the counter to the clock pulse input of the digital circuit and for delivering the digital stimulus signal to the stimulus input of the digital circuit in synchronism with the clock pulses coupled to the clock pulse input. An analyzing device has a first input arranged for receiving the digital test signal from the digital circuit and a second input connected for receiving the same number of clock pulses coupled to the digital circuit. The analyzing device is arranged for compressing and analyzing the test signal for errors. A device is provided for imparting a time delay of .tau. seconds to the clock pulses received by the analyzing means.

REFERENCES:
patent: 3976864 (1976-08-01), Gordon et al.
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patent: 4519078 (1985-05-01), Komonytsky
patent: 4534030 (1985-08-01), Paez et al.
R. C. Dixon, "Spread Spectrum Systems", Wiley & Sons, New York, 1976, pp. 54-55 and pp. 80-85.
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Scrambler/Descrambler IC SH100 B485, Siemens OEM Products for Telecommunications, 1.82, (4 pages).
F 100 K ECL Data Book of Fairchild 1982 (F100131 Triple D Flip-Flop (pp. 3-47-3-52).
F 100K ECL Data Book of Fairchild 1982 (F100102 Quint 2-Input OR/NOR Gate).

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