Circuit arrangement for telecommunications systems, particularly

Details Circuit arrangement for telecommunications systems, particularly Circuit arrangement for telecommunications systems, particularly

1984-07-19

1986-12-02

Fleming, Michael R.

Excavating

G06F 1110

Patent

active

046270590

ABSTRACT:
A dynamic memory system is connected to a data bus via a buffer. A parity evaluator is provided for monitoring air-free storage and is also connected to the data bus, the parity evaluator supplying a first parity bit to the memory upon storage of information incoming from the data bus and from a second parity bit upon emission of stored information and transmission thereof via the data bus, the parity evaluator comparing the second parity bit to the first parity bit.

REFERENCES:
patent: 4020459 (1977-04-01), Coomer
patent: 4360917 (1982-11-01), Sindelar et al.
patent: 4429391 (1984-01-01), Lee
patent: 4528665 (1985-07-01), Burns
patent: 4528666 (1985-07-01), Cline
Rowe H. L., "Parity on Bidirectional Microprocessor Bus", IBM Technical Disclosure Bulletin, vol. 21, No. 1, Jun. 1978, pp. 377-378.

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