Circuit arrangement for synchronizing the units in the switching

Details Circuit arrangement for synchronizing the units in the switching Circuit arrangement for synchronizing the units in the switching

1987-12-15

1989-07-11

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

375108, H04J 306

Patent

active

048478369

ABSTRACT:
Circuit arrangement for synchronizing the units in the switching exchanges and repeaters of a time-division multiplex transmission system. In time-division multiplex transmission systems a central control device (first unit) is frequently employed to process messages to be transmitted. For a regular mode of operation, the second units provided for the different functions require a plurality of clocks which are phase-synchronized with the clocks of the first unit. For this purpose either a plurality of clock lines between the first unit and the peripherals (second units) are provided or clocks are transmitted through two clock lines at the highest and lowest clock rates and synchronized with the frequency divider arranged in the peripherals (second units) in a master-slave relationship. In order to guarantee phase-coincidence during the frequency division and to include also short-term, non-synchronous conditions, the clock having the lowest clock rate and the clock having the highest clock rate generated by the frequency dividers arranged in the two units combined. The circuit complexible for this combining circuit is low and requires only one exclusive-OR circuits and an OR-circuit for each unit. The circuit arrangement according to the invention is preferably inserted in the device for converting signalling characters of the PCM 30 F time-division multiplex transmission system.

REFERENCES:
patent: 4147891 (1979-04-01), Roos
patent: 4606022 (1986-08-01), Suzuki et al.
patent: 4700357 (1987-10-01), Ast
P. Grotemeyer et al., "Das Systemgerat PCM 30 F", TE KA DE Technische Mitteilungen (1982), pp. 20-27.

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