Circuit arrangement for switching a digital service channel thro

Details Circuit arrangement for switching a digital service channel thro Circuit arrangement for switching a digital service channel thro

1990-07-13

1992-04-21

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 97, 3701053, 3701101, H04J 308, H04B 336

Patent

active

051074885

ABSTRACT:
A circuit arrangement for switching an externally accessible service channel, formed by additional bits within a digital data signal, contains an output circuit, which shifts the service-channel bits in time as soon as there is a threat of phase coincidence of a receive clock derived from the data signal with the transmit clock generated with an identical or slightly different frequency. Errors produced by an unclear assignment of the service-channel bit to the transmit clock are prevented in this way. The output circuit contains a buffer, a phase detector, and a changeover switch driven by the phase detector. To produce the time shift, the buffer clock is fed to the buffer via an inverter (I) interposed by the changeover switch. A second solution provides for a direct switching of the service signal and the interposition of the buffer clock with the inverted receive clock only during periods in which there is a threat of phase coincidence between the receive clock and the transmit clock.

REFERENCES:
patent: 4667319 (1987-05-01), Chum
patent: 4876683 (1989-10-01), Suzuki
patent: 4878219 (1989-10-01), Kaufman et al.
patent: 4935920 (1990-06-01), Taniguchi et al.
patent: 5018135 (1991-05-01), Ashi et al.

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