Circuit arrangement for simulating a resistive elementary two po

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G06F 738

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047165375

ABSTRACT:
A wave two port circuit arrangement for simulating a resistive elementary port two device for use in a wave digital filter. First and second ports are each arranged for receiving input and output signals. A summing device is connected to the first and second ports and produces a sum signal which represents the sum of the input signals present at the first and second ports. A multiplier is connected to the summing device and to one of the first and second ports for producing a negatively scaled sum signal and feeding it to the one port as part of the output signal present at that port.

REFERENCES:
patent: 3967099 (1976-06-01), Fettweis
patent: 4061905 (1977-12-01), Fettweis
patent: 4095276 (1978-06-01), Verkroost et al.
patent: 4192008 (1980-03-01), Mandeville
patent: 4344148 (1982-08-01), Brantingham et al.
patent: 4475229 (1984-10-01), Frese
"Wave Digital Filter Hardware Structure", Stuart Lawson, IEE Proc., vol. 128, Pt. 6, #6, pp. 307-312, Dec. 1981.
"Class of Wave Digital Filters Consisting Only of Adders and Multipliers", Nouia, Electronics Letters, vol. 12, #19, pp. 500-501, 9/16/76.
Alfred Fettweis et al, IEEE, "On Adaptor for Wave Digital Filters", vol. ASSP-23, No. 6, Dec. 1975, pp. 516-525.
A. Fettweis, "Digital Filter Structures", AEU Band 25, (1971), Heft 2, pp. 79-89.

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