Circuit arrangement for sensing errors in bit patterns

Details Circuit arrangement for sensing errors in bit patterns Circuit arrangement for sensing errors in bit patterns

1998-04-16

2001-02-13

Kizou, Hassan (Department: 2662)

Multiplex communications

Diagnostic testing

Fault detection

C370S252000, C714S706000, C714S819000

Reexamination Certificate

active

06188672

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a circuit arrangement for sensing errors in bit patterns for recording the occurrence in time, precisely to a bit, of transmission errors in a binary test signal, in particular for plotting a bit-error signal sequence produced by a comparator circuit on the basis of a test signal and a substantially identical reference signal.
RELATED TECHNOLOGY
It is generally known that bit-error measuring units transmit quasi-randomly distributed binary signal sequences, or pseudo random binary sequences (PRBS), as measuring signals over a measuring transmission path. These sequences are then synchronized on the receiving side to an identically generated PRBS and compared on a bit-by-bit basis. This comparison yields a further binary signal sequence, in which one signal state signifies conformity, and the other, deviation. This binary signal sequence, referred to as a bit-error pattern, represents an exact image of the disturbance response of the transmission path.
This binary signal comparison process has been generally limited to adding the binary data at the comparator output and deriving the so-called bit-error rate or bit-error number therefrom. Although information about the bit-error pattern is retained, important information about the position of the bit errors within the binary signal sequence is lost. When the bit error pattern is detected, each bit error and the instant of its occurrence are registered. However, due to the tremendous amount of data, it is impossible to record the entire binary signal sequence from the comparator. It has therefore been a goal to diminish redundancy in a detected bit error pattern sufficiently to permit continuous data registration without loss of data.
The known recording method, designed for transmission rates of up to 140 mbit/s, is limited to plotting those sections of the binary signal sequence which represent the bit error pattern, namely only those containing the bit errors. See Annual Report 1981 of the Research Institute of the DBP at FTZ, p. 29. To determine the bit errors under this method, sections of signal which are 32 bits in length are formed. Rather than checking each bit of the binary signal sequence individually, the 32 bit-length sections are analyzed for the presence of bit errors. This prolongs by a factor of 32 the time available for testing and response. The method permits a high processing rate to be achieved using components of moderate speed.
According to the known method, a section is stored when it contains one or more bit errors. When a section is error-free, it is ignored. To determine the position of the stored sections in the data stream, the current reading of a clock-pulse counter is stored along with every section. The clock-pulse counter continuously counts the data cycle, beginning with the start of measurement.
In addition to bit-error pattern sections, failure signals which indicate failure of the measuring path through AIS/duration-0 (alarm indication signal) and synchronism losses (slip) are recorded. After being buffered to compensate for different data velocities, all of these data are stored in a binary block-oriented format on a storage medium. The resulting bit-error pattern may be represented off-line in the form of a numerical sequence, but only after the measurement is concluded, and with computer support.
Off-line representation of the bit-error pattern makes use of two variables, “error length” and “error interval”. Error length signifies the number of bits, in direct succession, that have been incorrectly transmitted, while error interval represents the number of bits, in direct succession, transmitted without errors. These definitions may be used to describe the bit error pattern as a sequence of numerical values representing the error lengths (F) and error intervals (G). This error length/error interval sequence is denoted hereinafter simply as the “F/G sequence.” The F/G sequence represents a meaningful measuring result that can be immediately utilized. Moreover, it forms the basis for a number of further analyses, which are directed to special evaluation goals.
One drawback of the known method is that considerable hardware outlay is required to recode the bit-error signal sequence into a complicated intermediate format. The detecting unit is as a result quite complex. The binary data in this recorded format cannot easily be read. They are represented in an unprocessed form as a dot matrix during an on-going measurement. Therefore, the data are only conditionally suited for monitoring the measurement, since interpreting them presupposes a detailed knowledge of the block format. Measurements of longer duration require the manual assistance of specialists, and thus a greater outlay for training and instruction.
To ensure that the measuring operation is not flawed because of measurement set-up errors, the usefulness of the first measuring results is checked before the continuous recording process is started. For this purpose, a so-called “quick look” unit is used off-line to check the results of a brief sample measurement.
Another disadvantage associated with the known method of partitioning the bit-error signal sequence into 32-bit segments is that failure signals are detected with limited accuracy rather than single-bit precision. Additionally, the measurement results are stored initially on an intermediate storage medium, rather than directly on disk. Non-volatile solid state memories are used as intermediate storage media. Only after the measurement operation is concluded is it possible to read the measuring data from the intermediate storage media, to transfer the data out of the block format into the F/G sequence, and to store the data on disk. An additional read device with software is required for the recoding operation.
SUMMARY OF THE INVENTION
An object of the present invention is to reduce the outlay required in terms of hardware for detecting bit error patterns, and to make immediately readable results available during the on-going measuring operation.
Another object on the present invention is to diminish redundancy in a detected bit error pattern sufficiently to permit continuous data registration without loss of data.
The present invention therefore provides a circuit arrangement for sensing errors in bit patterns for plotting the occurrence in time, precisely to a bit, of transmission errors in a binary test signal, in particular for plotting a bit-error signal sequence (BFS) produced by a comparator circuit (
3
) on the basis of a test signal and a substantially identical reference signal. The present invention is characterized by a pulse-generating device (
5
), which is fed the bit-error signal sequence (BFS) and which generates a pulse (IS) in response to every signal change; a counting device (
11
), which increments a counter as a function of a supplied bit timing (BT) and resets it to the count value 1 when the pulse (IS) from the pulse-generating device (
5
) is applied; a buffer device (
13
) linked to the outputs of the counting device (
11
), said buffer device (
13
) buffering the counter content of the counting device (
11
) in response to the application of a pulse (IS); and an evaluation device (
17
,
19
,
23
), which is fed the buffered counter contents.
The F/G sequence is produced directly from the bit-error signal sequence of the comparator device in that a counting device alternately counts directly successive bits of the same signal state. A pulse having a duration of one clock-pulse period is generated with every signal change at the comparator output by a pulse-generating device, said pulse terminating the bit counting in the counting device for the current element of the F/G sequence. In addition, the pulse causes the counter content to be loaded into a buffer device and the counter to then be erased. The pulse also causes the first bit of the next element to be counted in that a “1” is loaded into the counting device.
The measuring data are passed through the buffer device primarily to compensate for

Affiliated with

Also associated with

Rating

Circuit arrangement for sensing errors in bit patterns does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit arrangement for sensing errors in bit patterns, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit arrangement for sensing errors in bit patterns will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2611776