Circuit arrangement for sampling a ternary signal

Details Circuit arrangement for sampling a ternary signal Circuit arrangement for sampling a ternary signal

1986-06-03

1987-10-13

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

375118, 328151, H04L 2534

Patent

active

047003596

ABSTRACT:
In a circuit arrangement for sampling a ternary signal, this ternary signal is divided by amplitude decision circuits into two binary signals and the binary sub-signals are sampled at m-times the rate of the symbol clock. The binary samples of each sub-signal are shifted through a shift register having at least m stages and intermediately stored in a buffer store for one period of the symbol clock. With the aid of a logic circuit it is then determined in which regions of the buffer store accumulations of identical binary values occur. Regions in which the accumulations always re-occur--the number of occurrences is checked by means of counters--are considered to be eyes of the ternary signal. In each clock period of the synbol clock, a sample falling within the eye of the ternary signal is transferred from each buffer store at an output of the circuit with the aid of a gate circuit.

REFERENCES:
patent: 3864529 (1975-02-01), Tracey et al.
patent: 4339823 (1982-07-01), Predina et al.

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