Circuit arrangement for routing signals between a master-slave p

Details Circuit arrangement for routing signals between a master-slave p Circuit arrangement for routing signals between a master-slave p

1982-12-22

1987-03-31

Shaw, Gareth D.

Boots, shoes, and leggings

380827, 379274, G06F 1120

Patent

active

046547843

ABSTRACT:
A plurality of switching modules, e.g. components of a digital telephone exchange, each include a pair of central processing units (CPUs) operating in master-slave relationship under the supervisory control of two support processors alos constituting a master-slave pair. Each support processor communicates via a respective bus with all switching modules by way of respective signal lines extending from that bus to one CPU of each pair. Each signal line includes two closely juxtaposed, cascaded interfaces each of which, in turn, has an externally and an internally accessible input/output (I/O) section. The externally accessible I/O section of each interface inserted in the active line between the master processor and the master CPU of any module is normally operational and communicates by an in-line link with the corresponding I/O section of the interface in cascade therewith. If that link breaks down, the connection is re-established through the hitherto nonoperational internally accessible I/O sections of these interfaces and of the two other interfaces paired therewith. In the event of a malfunction of an interface tied to the bus of the master processor, a coupler temporarily interconnects the two buses during a time slot allocated to the affected module in order to switch the connection to the in-line link extending between the other two cascaded interfaces serving that module. A malfunction of the master CPU of a module, or of the interface directly connected thereto, causes a similar switchover with assignment of the master role to the other CPU but without change in the master/slave relationship of the support processors.

REFERENCES:
patent: 3681694 (1972-08-01), Sarati
patent: 3882455 (1975-05-01), Heck et al.
patent: 4011542 (1977-03-01), Baichtal et al.
patent: 4030069 (1977-06-01), Henrickson et al.
patent: 4059736 (1977-11-01), Perucca et al.
patent: 4081611 (1978-03-01), Bovo et al.
patent: 4144407 (1979-03-01), Zaffignani et al.
patent: 4257099 (1981-03-01), Appelt
patent: 4365247 (1982-12-01), Bargeton et al.
patent: 4499336 (1985-02-01), Krikor et al.
"Reliable Systems: Design and Tests", Eric J. Lerner, IEEE Spectrum (Oct. 1981).

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