Circuit arrangement for removing stuff bits

Details Circuit arrangement for removing stuff bits Circuit arrangement for removing stuff bits

1991-10-25

1994-01-18

Kuntz, Curtis

Pulse or digital communications

Spread spectrum

Direct sequence

370102, H04L 700

Patent

active

052805026

ABSTRACT:
The described circuit arrangement for removing stuff bits from a frame-structured signal which is available in n parallel bits, comprises a memory circuit (2) which is supplied with the parallel bits (1b). The memory circuit (2) is followed by a controllable selection circuit (3) having n outputs (3a). A control circuit (9) produces control signals (9b, 9c), which determine which bits stored in the memory circuit are transported to the n outputs (3a) of the selection circuit (3). The memory circuit (2) comprises only n delay elements by which each of the n parallel bits (1b) is delayed for the duration of one bit. So as to provide that n delay elements will be sufficient, the control circuit (9) is to block at predetermined time intervals the acceptance of new bits in one or a plurality of delay elements.

REFERENCES:
patent: 4596026 (1986-06-01), Cease et al.
patent: 4899339 (1990-02-01), Shibagaki et al.
patent: 5030951 (1991-07-01), Eda et al.
patent: 5091907 (1992-02-01), Wettengel
patent: 5132970 (1992-06-01), Urbansky

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