Circuit arrangement for regenerating an input signal...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Regenerating or restoring rectangular or pulse waveform

Reexamination Certificate

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C327S344000, C327S345000, C327S363000

Reexamination Certificate

active

06194934

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit arrangement, in particular for wireless telecommunication apparatuses according to the DECT standard, for the regeneration of an input signal containing characteristic digital data sequences.
2. Description of the Prior Art
In today's data processing installations, communication apparatuses and communication systems, the transmission, storing and processing of data increasingly takes place with the aid of digital technology. Data is thereby stored as sequences of discrete values. This digital coding is based in most cases on a binary representation in which the allowed range of values is limited to two different discrete values, designated as a rule as “HIGH” or “1,” and “LOW” or “0.” The individual elements positions in a data sequence coded in this way are designated in binary coding as “bits” (from binary digit). However, digital representations are also used with three or more different discrete values in the allowed value range.
If a sequence of digital values is represented as an electrical signal, a signal curve results from a sequence of signal impulses that respectively represent a position of the underlying digital value sequence. In the ideal case, all impulses representing the same digital value are thereby identical to one another and differ clearly, e.g. in form or level height, from impulses that represent other digital values. In this way, each digital value is reversibly and unambiguously allocated to a specific type of impulse.
In digital technology, one very often makes use of a coding in the form of what are called “rectangular impulses” that are equally long among themselves, whereby each impulse includes a signal level that is constant within a range of tolerance and whose height characterizes it. For the signal level, only discrete values are thereby allowed, whose number is equal to the number N of different values in the underlying digital range of values, whereby each digital value is reversibly and unambiguously allocated to one of the signal levels.
In the transmission, storing or processing of digitally coded data with the aid of (generally electrical or optical) signals, in practice, disturbances constantly occur that lead to deviations from the ideal signal curve. If these deviations, e.g. due to repeated transmission of a signal, become too large, the underlying digital value sequence can no longer be recovered unambiguously from the signal and malfunctions may occur. In general, this problem is countered by regenerating the corresponding signals, e.g. after a transmission via a transmission path or during the reading out from a memory, using corresponding means, whereby the original signal curve is reproduced to the greatest possible extent.
From EP 0 133 067 A1, e.g., such an apparatus is known for the regeneration of a readout signal from optical storage diskettes, which includes for the correction of a readout clock signal a deformation circuit connected after a readout processor.
The regeneration of digital signals is also used in wireless telecommunication apparatuses operated, for example, according to the digital DECT standard, in order to free the signals transmitted via radio between the base station and the mobile part (or, respectively, the mobile part and the base station) from disturbances that occur thereby.
A corresponding circuit arrangement for DECT systems as shown in
FIG. 1
is disclosed in DE 42 36 774 C2. The binary-coded signal to be regenerated, designated the input signal UE in the following, is thereby supplied to an analog comparator K, which compares it with a reference level U
IG
and outputs, at its output, the signal U
A
, regenerated in a sequence of equally long rectangular impulses with identical bit structure. The reference level U
IG
is obtained by means of segment-by-segment integration of the input signal U
E
by means of an integration element IG.
The fact is thereby exploited that, according to the DECT standard, in each transmission channel the synchronous initializer word, which includes the first 16 bits of a transmission frame consisting of 420 bits and which serves for synchronization together with the synchronous acknowledgment word including the subsequently following 16 bits, represents a characteristic data sequence. It consists of a periodic alternating bit sequence of HIGH and LOW values, which for the transmission direction “mobile station—base station” begins with “1010 . . . ” and for the reverse transmission direction “base station—mobile station” begins with “0101 . . . . ” The integration of an input signal U
E
, as shown in
FIG. 3
a
, respectively extends only to this characteristic bit sequence and is broken off with the aid of a switch S
1
, driven by a checking apparatus CTRL, if after the synchronous initializer word two identical bit values follow one another in succession for the first time. In this way, there results, as shown in
FIG. 3
b
, a reference level U
IG
, approximately at the height of the average value U
DC
of the HIGH and LOW levels of the input signal U
E
, which is stable during the regeneration of the subsequently following signal curve. However, a disadvantage of the disclosed solution is that the first bit value identical to the immediately preceding one is not recognized until integration has already taken place over the associated signal impulse, whereby a reference level U
IG
results that is offset in relation to its previous value U
DC
. This undesired offset UOFF of the reference level must then subsequently be corrected, via an adder component ADD, by means of an offset compensation unit OK, connected with a switch S
2
. The magnitude of the offset U
OFF
to be corrected is thereby dependent on the level of the input signal U
E
.
If, as is also the case for the DECT wireless transmissions, this input signal U
E
arises by means of the demodulation of a radio signal, the magnitude of the offset U
OFF
to be compensated is dependent on the level of the demodulated signal U
E
, and thus, according to the type of the modulation, depends, e.g., on the amplitude range or the frequency range of the transmitter. The modulation range of a transmitter can thereby include a wide range of variation.
At least in DECT wireless telecommunication apparatuses, there is a further disadvantage because, due to the synchronous initializer words inverted with respect to one another, the polarity of the required compensation must be opposed for the two directions of transmission “mobile station—base station” and “base station—mobile station.”
An object of the present invention is thus to indicate a circuit arrangement, improved in relation thereto, for the regeneration of an input signal containing characteristic digital data sequences, in which the cited disadvantages are avoided.
SUMMARY OF THE INVENTION
This object is solved by means of a circuit arrangement for the regeneration of an input signal containing characteristic digital data sequences with N>1 different allowed discrete values per digital position which includes:
conversion means that produce a regenerated digital output signal from the comparison of the input signal with at least N−1 reference levels,
at least one integration element for the obtaining of the at least N−1 reference level by means of integration of the segments of the input signal that consist of the characteristic data sequences,
a drivable switching means for the activation or, respectively, deactivation of the input signal,
a checking means that respectively activates the integration process by driving the switching means at the beginning of a characteristic data sequence and, when the end of the data sequence is recognized, deactivates it in order to avoid a shifting of the at least N−1 reference levels, as well as
at least one delay element, via which the supplying of the input signal to the at least one integration element takes place with a delay in relation to the supplying of the input signal to the conversion means

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