Circuit arrangement for reducing the settling time of logarithmi

Details Circuit arrangement for reducing the settling time of logarithmi Circuit arrangement for reducing the settling time of logarithmi

1986-09-26

1988-04-12

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307543, 307549, 307492, 307311, 3075421, 328145, H03K 500, H03K 342, H03K 1756, G06G 724

Patent

active

047376686

ABSTRACT:
A circuit arrangement for reducing the settling time of amplifiers to which photoelectronic components are connected. A control circuit is provided which, operating in conjunction with components of this circuit arrangement, prevents the parasitic capacitance of the photoelectronic component from being charged up when the circuit arrangement is connected to the operating voltage.

REFERENCES:
patent: 4188551 (1980-02-01), Iwasaki et al.
patent: 4639134 (1987-01-01), Bletz

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