Circuit arrangement for recording the addresses of storage cells

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371 21, 371 13, G06F 1110

Patent

active

046213643

ABSTRACT:
To record the address of a storage cell that has contents that are erroneous with respect to the coding, a memory configuration, connected by means of a bus line system with a central control unit, is equipped with a register in the recording cells of which can be written the address of the selected storage cell which is transmitted over the bus line system during the performance of a read cycle in the memory's configuration. Each memory contents that are read out from one of the storage cells in the course of such a read cycle are checked in an error-recognition circuit for the existence of a coding error. When a coding error of this kind is recognized, the error recognition circuit then emits an appropriate error signal. In response to such an error signal, a control device locks out the register for the reception of another address transmitted over the bus line system. In addition, this control device causes the central control unit to evaluate the address last written into the recording cells of the register as the address of a faulty storage cell.

REFERENCES:
patent: 4532628 (1985-07-01), Matthews
patent: 4535455 (1985-08-01), Peterson
patent: 4542454 (1985-09-01), Breich
patent: 4549295 (1985-10-01), Purvis

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