Circuit arrangement for reconstructing noise-affected signals

Details Circuit arrangement for reconstructing noise-affected signals Circuit arrangement for reconstructing noise-affected signals

1983-07-29

1985-05-14

Mullins, James B.

Amplifiers

Signal feedback

Combined with control of bias voltage of signal amplifier

330149, 455223, H03B 104

Patent

active

045175187

ABSTRACT:
An analog input signal is applied to a timing circuit (2) for generating a sampling pulse in response to an impulse noise introduced to the signal and also to a first sample-and-hold circuit (7, 8, 9) through a buffer amplifier (6). The first sample-and-hold circuit includes a capacitor (7) and a switch (8) for applying the analog signal to the capacitor to develop a voltage therein which keeps track of the waveform of the analog signal in the absence of the sampling pulse and holding the voltage in response to the sampling pulse. A differentiator (11) is coupled in a feedback loop from the output of the first sample-and-hold circuit for generating a signal representative of the slope ratio of the analog signal. A second sample-and-hold circuit (15) is provided in the feedback loop for sampling and holding the slope ratio signal in response to the sampling pulse. Further included in the feedback loop is a bidirectional constant current source (20) which provides constant current charging and discharging of the capacitor (7) in response to an output signal from the second sample-and-hold circuit (15).

REFERENCES:
patent: 4076969 (1978-02-01), Sacks
patent: 4305042 (1981-12-01), Tanaka et al.
patent: 4311963 (1982-01-01), Watanabe

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