Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2000-06-14
2002-09-17
Jackson, Stephen W. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S111000, C361S118000, C361S091100
Reexamination Certificate
active
06452768
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a circuit arrangement for the protection of integrated circuits against electrostatic discharges on a component of such integrated circuits.
BACKGROUND INFORMATION
It is known that electrostatic discharges can occur in the manufacture of integrated circuits, in the case of hybrid processes in particular, in which various production methods, for example, the joint production of bipolar and MOS transistors is to take place. These electrostatic discharges result in voltage peaks which can result in destruction of the integrated circuits.
SUMMARY OF THE INVENTION
To protect integrated circuits, it is possible to use MOS protective transistors, its gate terminal is connected to the source terminal of the protective transistor via a break distance of an additional MOS transistor. A voltage pulse brought about by an electrostatic discharge is present at the drain terminal of the protective transistor and at the gate terminal of the second MOS transistor. In this connection, use is made of the effect that, with varying gate voltage, the breakdown voltage of an MOS transistor has a minimum at approximately 0.5 volts above a threshold voltage of the MOS transistor. This breakdown voltage represents the operating point for an effective protection against electrostatic discharges. If a voltage pulse now occurs as the result of an electrostatic discharge, the gate voltage of the protective transistor is raised briefly above the threshold voltage as the result of a gate-drain capacitance. At the same time, however, the second MOS transistor also switches through since the voltage pulse is present at its gate terminal so that the gate voltage of the protective transistor drops again below the threshold voltage. Thus the electrostatic discharge passes through the operating point of the protective transistor only briefly during the occurrence of the voltage pulse, thus resulting in an unreliable design.
The circuit arrangement according to the present invention offers the advantage that, in addition to ensuring an effective protection against electrostatic discharges in a simple manner, it is possible to adjust the operating point of the protective transistor in a controlled manner for the total duration of an electrostatic discharge pulse. Due to the fact that at least one diode is connected in forward direction between the source terminal of the second MOS transistor and the source terminal of the MOS transistor, the effect of the diode, which is known per se, can be used to maintain voltages at a nearly constant level. As a result, the gate voltage of the MOS transistor is maintained above the threshold voltage for the entire duration of the pulse of the electrostatic discharge, making it possible to reduce the voltage pulse of the electrostatic discharge in a controlled manner via the protective transistor.
Instead of the diode, a suitable Zener diode can also be connected in reverse direction.
REFERENCES:
patent: 5543650 (1996-08-01), Au et al.
patent: 5625522 (1997-04-01), Watt
patent: 5959820 (1999-09-01), Ker et al.
patent: 44 39 125 (1996-05-01), None
Mack WD et al; New ESD Protection Schemes for BICMOS Processes with Application to Cellular Radio Designs; Proceedings of the International Symposium on Circuits and Systems, San Diego, May 10-13, 1992; Institute of Electrical and Electronics Engineers, pp. 2699-2702.
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