Circuit arrangement for producing a fluctuation-free d-c voltage

Details Circuit arrangement for producing a fluctuation-free d-c voltage Circuit arrangement for producing a fluctuation-free d-c voltage

1986-04-16

1987-09-15

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307304, 307491, 323313, H03K 301, G05F 316

Patent

active

046941991

ABSTRACT:
Circuit arrangement for producing a fluctuation-free d-c voltage level of a d-c supply voltage having a voltage divider of MOS transistors at the supply voltage, the voltage divider including a first series connection of a plurality of MOS transistors located in a branch between a tap for a reference voltage and a reference-potential input, and a second series connection of MOS transistors located between a d-c supply-voltage input and the reference-potential input and being driven jointly by the reference voltage at the tap of the voltage divider, the first series connection including at least four transistors, and including an MOS transistor drivingly connected to the d-c supply-voltage input and further connected in the second series connection of MOS transistors located between the d-c supply-voltage input and the reference-potential input.

REFERENCES:
patent: 3806742 (1974-04-01), Powell
patent: 3823332 (1974-07-01), Feryszka et al.
patent: 3975649 (1976-08-01), Kawagoe et al.
patent: 4024415 (1977-05-01), Matsuura
patent: 4300061 (1981-11-01), Mihalich et al.
patent: 4375596 (1983-03-01), Hoshi
patent: 4446383 (1984-05-01), Concannon et al.
patent: 4451744 (1984-05-01), Adam
patent: 4453121 (1984-06-01), Noufer
Askin et al., "FET Device Parameters Compensation Circuit", IBM Tech. Bulletin, vol. 14, No. 7, pp. 2088-2089, Dec. '71.
Greenberg et al., "A Bias Circuit Compensated for Threshold and Supply Variations", IBM Tech. Bulletin, vol. 16, No. 1, 6/73.

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