Circuit arrangement for processing sampled analogue electrical s

Details Circuit arrangement for processing sampled analogue electrical s Circuit arrangement for processing sampled analogue electrical s

1988-12-16

1990-01-30

Wong, Peter S.

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

323316, G05F 324

Patent

active

048975966

ABSTRACT:
A circuit arrangement for processing sampled analog electric signals includes a low voltage cascode current mirror circuit arrangement having an input branch comprising first and second FETs (T1,T3) and an output branch comprising third and fourth FETs (T2,T4). In order to provide the correct bias potential of V.sub.t +2V.sub.on at the gate electrodes of the second and fourth FETs (T3,T4) a second output branch comprising two further FETs (T5,T6) and a further current mirror circuit comprising two other FETs (T7,T8) pass a current through a diode connected FET (T9) so that it produces a voltage V.sub.t +V.sub.on. If this current is equal to the input current, then the diode connected FET (T9) is constructed to have a gate width to length ratio of one quarter of that of the cascode connected transistors (T3,T4). The current mirror circuit may be incorporated into current scaling and current memory circuits for signal current manipulation.

REFERENCES:
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Fisher et al., "A Highly Linear CMOS Buffer Amplifier", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 3, Jun. 1987, pp. 330-334.

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