Circuit arrangement for phase locked loop, and phase locked...

Details Circuit arrangement for phase locked loop, and phase locked... Circuit arrangement for phase locked loop, and phase locked...

2007-10-16

2007-10-16

Urban, Edward F. (Department: 2618)

Telecommunications

Receiver or analog modulated signal frequency converter

With particular receiver circuit

C455S343100, C455S260000

Reexamination Certificate

active

10429493

ABSTRACT:
The invention relates to a circuit arrangement (4) for a PLL to be used in a terminal (50) of a time division cellular network. In a PLL according to the invention, the control voltage (32a) to a VCO (33) in the PLL is kept at a desired value also during time slots in which the terminal is not receiving or transmitting messages. The settling time for a PLL according to the invention is shot and the spurious effects caused by the power up thereof are small. The invention further relates to a method of operation for a PLL.

REFERENCES:
patent: 4893094 (1990-01-01), Herold et al.
patent: 5202906 (1993-04-01), Saito et al.
patent: 5355098 (1994-10-01), Iwasaki
patent: 5379002 (1995-01-01), Jokura
patent: 5475877 (1995-12-01), Adachi
patent: 5521947 (1996-05-01), Madsen
patent: 5523724 (1996-06-01), Assar et al.
patent: 5581214 (1996-12-01), Iga
patent: 5714912 (1998-02-01), Fiedler et al.
patent: 5767791 (1998-06-01), Stoop et al.
patent: 5842029 (1998-11-01), Conary et al.
patent: 6009319 (1999-12-01), Khullar et al.
patent: 6163585 (2000-12-01), Yamawaki et al.
patent: 6169912 (2001-01-01), Zuckerman
patent: 6215362 (2001-04-01), Feng et al.
patent: 6226274 (2001-05-01), Reese et al.
patent: 6265947 (2001-07-01), Klemmer et al.
patent: 6407600 (2002-06-01), Lu et al.
patent: 6472915 (2002-10-01), Moyal et al.
patent: 6522204 (2003-02-01), Rennick
patent: 6608510 (2003-08-01), Yamawaki et al.
patent: 6611160 (2003-08-01), Lee et al.
patent: 6646512 (2003-11-01), Abassi et al.
patent: 6765977 (2004-07-01), Adams et al.
patent: 6788924 (2004-09-01), Knutson et al.
patent: 6795516 (2004-09-01), Takekawa et al.
patent: 2002/0077074 (2002-06-01), Piazza
patent: 2002/0132598 (2002-09-01), Saito
patent: 2002/0159541 (2002-10-01), Tahtinen
patent: 2003/0001681 (2003-01-01), Asikainen et al.
patent: 2003/0006848 (2003-01-01), Cordoba
patent: 2003/0060176 (2003-03-01), Heinonen et al.
patent: 2003/0189991 (2003-10-01), Puccio et al.

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