Circuit arrangement for performing rapid sortation or selection

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3401462, G06F 700

Patent

active

046513019

ABSTRACT:
The invention is directed to a circuit arrangement for rapid sortation or selection of at least three digital values according to rank. In the circuit arrangement, the input channels are directly interconnected via digital comparators or arithmetic logic units. The outputs of the digital comparators or arithmetic logic units are connected to a gate-logic circuit or a ROM table controlling data selectors for the transfer of selected values or a network of data selectors for the sortation of all input values.

REFERENCES:
patent: 3740538 (1973-06-01), Hemphill
patent: 4410960 (1983-10-01), Kasuya
patent: 4567572 (1986-01-01), Morris et al.

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