Circuit arrangement for noise suppression in binary data signals

Details Circuit arrangement for noise suppression in binary data signals Circuit arrangement for noise suppression in binary data signals

1986-03-06

1987-06-09

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

375102, 360 39, 307358, 328163, H03K 5153, H04B 112

Patent

active

046726357

ABSTRACT:
For suppressing faults in binary data signals, two circuit branches respectively allocated to one of the polarities of the data signals and each comprising an integrator element and a comparator are provided. The integrator elements, triggered by an edge change of the data signals into the allocated polarity, regardless of a following edge change, acquire the signal components of this polarity up to a prescribed threshold. In response to a corresponding output signal of the following comparator, both integration elements are reset in common. The comparator output signals are also supplied to the set or reset inputs of a bistable switch means which outputs the noise-deinfested data signals.

REFERENCES:
patent: 3473131 (1969-10-01), Perkins
patent: 4137504 (1979-01-01), Simmons
patent: 4479266 (1984-10-01), Eumurian et al.
patent: 4535294 (1985-08-01), Erickson et al.
IBM Technical Disclosure Bulletin, vol. 15, No. 2, Jul. 1972, Ernisse et al., "Multiplexing Amplitude Pointer with Digital Data to Enhance Error Correction", pp. 643-645.
IBM Technical Disclosure Bulletin, vol. 20, No. 2, Jul. 1977, Luhrs et al., "Adaptive Equalization for Digital Recorder Readback Circuits", pp. 518-520.
Japanese application No. 55-44628 of Hideo Nishijima, "Noise Rejecting Circuit", vol. 6, No. 22 (P-101), Feb. 9, 1982.
"Applied Ideas", 8029 Electronic Engineering, vol. 54, (1982), Sep., No. 669, London, Great Britain, p. 24.

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