Circuit arrangement for monitoring an output load

Details Circuit arrangement for monitoring an output load Circuit arrangement for monitoring an output load

1999-03-04

2001-08-21

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Converter compensation

C341S144000

Reexamination Certificate

active

06278390

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a circuit arrangement for monitoring an output load of a digital-to-analog current converter which supplies an analog output current in dependent on a digital comparison data word, which output current is applied to a first resistor and, if present, the output load arranged in parallel with said first resistor.
In known circuit arrangements of this type the output voltage appearing across the resistor or the resistors is checked only once, generally when the arrangement is switched on, which arrangement can, for example, form a part of a PC. For this purpose, a given data word is applied and the voltage drop across the resistors is compared with a reference voltage. By means of this one-time comparison it is merely possible to detect whether or not the output load is present at that time. Its magnitude cannot be monitored. If the output load is removed during operation of the circuit arrangement, this cannot be detected.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a circuit arrangement of the type defined in the opening paragraph, which enables the output load to be monitored continuously.
According to the invention this object is achieved in that there has been provided a digital first comparator which compares the data words applied to the digital-to-analog current converter with at least one comparison data word. An analog second comparator compares the voltage drop across the first resistor with at least one reference voltage and applier to output signal to a flip-flop. A comparison circuit monitors the magnitude and/or the presence of the output load in dependence on the output signals of the first comparator and the flip-flop.
This circuit arrangement in accordance with the invention makes it possible to carry out a continuous check of the output load, i.e. to monitor continuously whether the output load is present and whether it has the prescribed magnitude.
For this purpose, the data words received by the digital-to-analog current converter during steady operation are applied to a digital first comparator, which compares these data words with a comparison data word. At any time and for every data word this comparison indicates whether this data word is greater or smaller than the comparison data word.
An analog second comparator compares the voltage drop across the first resistor or the parallel arrangement of the two resistors with at least one reference voltage.
The magnitude of the voltage drop depends on whether the external output load is arranged in parallel with the first resistor and whether it has the prescribed magnitude. The comparison of the two voltages by means of the comparator and the conversion of its output signal into a digital signal by means of a flip-flop results in a signal which provides a continuous indication of which of the two voltage values is greater.
Thus, the digital output signals of the digital first comparator and of the flip-flop basically furnish similar information. In the case of the prescribed resistance and a correctly corrected output load, both output signals should yield substantially the same duty cycles, i.e. approximately equal time intervals in which the data words or the output voltage are greater than the comparison values and time intervals in which they are smaller than the comparison values. This processing is effected by means of a digital comparison circuit capable of drawing conclusions about the presence and magnitude of the output load from these duty cycles.
Particularly in order to improve the detection of the magnitude of the output load several data words and reference voltages of different magnitudes can be provided, thus enabling a finer graduation of the digital words and analog voltages to be obtained.
If desired, the comparison described above can be effected continuously during normal operation of the circuit arrangement and of the digital-to-analog current converter, thus enabling the presence and the magnitude of the output load to be monitored continuously by means of the comparison circuit. A removal of the output load can then be detected immediately also during operation of the circuit arrangement. Furthermore, if the circuit arrangement has been put into operation without an output load, it is also possible to immediately detect a correct connection of the output load during subsequent operation. If the circuit arrangement is used, for example, in a personal computer, checking is effected not only during booting of the computer but also during steady operation of the computer.
In the case of the dimensioning used in an embodiment of the invention defined in claim
2
a conclusion about the correct connection and magnitude of the output load can be drawn merely by direct comparison of the duty cycles of the two signals applied to the comparison circuit.
In the further embodiments defined in claims
3
,
4
and
5
the signals to be compared can, if required, be preprocessed before they are applied to the comparison circuit. In this way, the signal delay in the digital-to-analog current converter can be compensated for or, if applicable, the signals can be smoothed and a detection of the duty cycles is already possible before the comparison circuit.
The circuit arrangement in accordance with the invention can be used advantageously for the conversion of video signals, for which further embodiments defined in claims
6
and
7
can be used advantageously.
In a further embodiment of the invention defined in claim
8
the result of the detection of the output load can be used to suppress or turn off the output signal of the digital-to-analog current converter. Thus, no output signal is supplied in the absence of the output load.
As is defined in claim
9
, this suppression of the output signal can be controlled advantageously by the comparison circuit.
Hereinafter, an embodiment of the invention will be described in more detail by way of example.


REFERENCES:
patent: 4928049 (1990-05-01), Pietrobon et al.
patent: 5825321 (1998-10-01), Park

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