Circuit arrangement for monitoring a clock-timed load

Details Circuit arrangement for monitoring a clock-timed load Circuit arrangement for monitoring a clock-timed load

1999-02-01

2001-03-06

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By presence or absence pulse detection

C327S018000, C327S037000, C327S057000, C327S060000

Reexamination Certificate

active

06198310

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a circuit arrangement for monitoring a load operated with a clock signal, a load signal being used for the monitoring. The present invention is usable in the field of motor vehicle electronics, for example.
BACKGROUND INFORMATION
In many fields, increasing use is being made of clock-timed systems for energy balance reasons. This applies in particular to the motor vehicle field, and, in that context, especially for the operation of inductive loads. In many fields it is also essential or at least advantageous to monitor these clock-timed systems while they are operating. A great variety of corresponding monitoring systems and circuit arrangements for monitoring are known.
U. Tietze and Ch. Schenk: “Halbleiter-Schaltungstechnik” (Semiconductor circuit technology), Springer-Verlag, Berlin, Heidelberg, N.Y., describes numerous basic electronic circuits. Reference is made at this juncture to the chapter “Schaltwerke (Sequentielle Logik)” (Switching mechanisms (sequential logic)) on pages 232 ff. of the 10th edition of the aforementioned book. On page 234 f., a D-flip-flop is described as an example of a basic circuit.
Braking systems implemented in motor vehicles may be clock-timed systems in which the circuit arrangement according to the present invention can be used, for example. German Patent Application No. 195 46 682 describes a hydraulic braking system for performing a driver-independent and wheel-selective braking action. German Patent Application No. 195 29 363 describes a hydraulic braking system of an ABSR system.
It is of course also possible to use the circuit arrangement according to the present invention in a pneumatic braking system.
What is problematic in terms of monitoring of a clock-timed load is that a load signal used for monitoring is also present as a clock-timed signal. In conventional arrangements, the clock-timed load signal that is to be monitored is connected to an input of a microcomputer or microcontroller. At each active clock phase, the microcomputer checks whether the clock-timed load signal to be monitored conforms to the required value.
A disadvantage of the conventional arrangements is that correspondingly fast inputs of the microcomputer must be made available for monitoring the clock-timed load signal. During each active clock phase (which in some cases can be very short), the microcomputer must check whether the clock-timed load signal that is present conforms to a given value. This requires a high level of circuit engineering complexity. Monitoring systems of this kind are correspondingly complex and cost-intensive to implement. A further disadvantage is that monitoring arrangements of this kind have high power consumption due to the high processing speed required.
SUMMARY OF THE INVENTION
It is an object of the present invention to make available a circuit arrangement for monitoring a load operated with a clock signal which has a simple and economical design and which reliably guarantees monitoring of the load even when active clock phases are short.
In accordance with an exemplary embodiment of the present invention, a circuit arrangement for monitoring a load operated with a clock signal is provided. The circuit arrangement includes a comparator having at least two inputs and one output, and a D-flip-flop having one clock input, one signal input, and one output. At least a first input of the comparator is coupled to the load signal. The output of the comparator is coupled to the signal input of the D-flip-flop. The clock input of the D-flip-flop is coupled to the clock signal. The output of the D-flip-flop delivers a monitoring signal. An advantage of this circuit arrangement is that with minimal circuit-engineering outlay, it makes available a quasi-static monitoring signal for fault situations and for fault-free operation. The requirement to make a fast microcomputer input available can thus be eliminated. Because of the characteristics of the D-flip-flop, the circuit arrangement according to the present invention reacts to the applied input signal, i.e., to the clock-timed load signal that is to be monitored, only during the active clock phases. A quasi-steady-state logic signal, which assumes the value of a logical one or a logical zero in accordance with the presence of a fault, is delivered at the output of the D-flip-flop. A further advantage is that the circuit arrangement inherently checks, during each phase of the clock signal, whether or not a fault is present. In particular, the circuit arrangement is capable of resetting an output signal that has been set (for example to logical one) because a fault has occurred, if the fault does not occur again in a subsequent clock cycle. Setting and resetting of the output signal are thus accomplished automatically in accordance with the presence of a fault situation or the presence of a normal operating state. The output signal made available by the circuit arrangement can be processed further by a control device or by a microcomputer.
In a braking system, for example, the further processing may be as follows: if the output signal indicates a fault, the corresponding function that is performed by the control device and for which the monitored load (in this case the valve) is necessary but faulty, can be deactivated. The control device can also go into a so-called emergency mode.
In a exemplary embodiment of the invention, a reference signal is applied to a second input of the comparator, this reference signal preferably being adjustable. This has the advantage that the load signal to be monitored can be monitored with reference to an arbitrarily adjustable reference signal. For example, with a circuit arrangement of this kind it is possible to monitor whether the load signal lies above or below an arbitrarily selected reference signal. It is particularly advantageous that the reference voltage is adjustable, since the reference signal can thereby be adapted to various loads. Moreover, the reference signal can also be adapted to various operating states of the load. This allows particularly reliable monitoring of the load to be achieved, in a manner adapted to each operating state. The reference voltage, in particular, the controllable reference voltage, can be made available by, for example, a voltage source, a voltage divider, or a current source with a connected load resistor.
In a further exemplary embodiment of the present invention, the reference signal is also a clock-timed signal. The advantage in this context is that the power consumption of the circuit arrangement is further reduced because the reference signal is clock-timed. It is furthermore advantageous that with this configuration, a clock-timed voltage is present at both inputs of the comparator, so that any initial transients compensate for one another.
In a further exemplary embodiment of the present invention, the comparator is a window comparator in which two different reference voltages are applied to two second inputs. This has the advantage that the load signal to be monitored can be checked as to whether it lies within a signal range defined by the two reference voltages. The flexibility of the circuit arrangement is thereby increased, and in particular it is possible to specify various fault types which affect the load signal in different ways.
In a further exemplary embodiment of the present invention, the load is an inductive load, in particular a valve in a motor vehicle, the load signal to be monitored being the current flowing through the load. It is advantageous in this context that the circuit arrangement according to the present invention can also be used with inductive loads. This eliminates, in particular, the large outlay in terms of circuit engineering that usually must be made for the monitoring of inductive loads, since conventional monitoring systems detect the load current in the free-running circuit with the load driver switched off, which leads to technical problems or inaccuracies because of the high voltage (which is higher than the supply

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