Circuit arrangement for in-circuit emulation of a...

Data processing: structural design – modeling – simulation – and em – Emulation – In-circuit emulator

Reexamination Certificate

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Details

C703S024000, C703S026000, C703S027000, C716S030000

Reexamination Certificate

active

06366878

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a circuit arrangement for in-circuit emulation of a microcontroller, and to a microcontroller for use therein.
When developing application systems with microcontrollers, it is necessary for the microcontroller to be operated in the application system itself, and for internal signals and states, which are not accessible in normal operation, to be guided outside and monitored for test purposes. In particular, there is a need to provide a possibility of access to the operating program of the microcontroller, which in normal operation is stored in an ROM memory which is not directly accessible from outside. The operating program can thereby be changed during the development phase. A service computer is used as user interface to the microcontroller. This technique is denoted as in-circuit emulation (ICE) of the microcontroller.
Production of a variant of a standard commercially manufactured microcontroller which is suitable for in-circuit emulation is problematical. To date, a bond-out version in which additional internal signals are guided outside and can thereby be tapped has been produced for this purpose. The outlay on production of the bond-out microcontroller is exceptionally high. By contrast with the standard commercially manufactured circuit, the bond-out version of the microcontroller is usually available only after substantial delay.
SUMMARY OF THE INVENTION
The object of the invention is to reduce the outlay for providing a microcontroller suitable for in-circuit emulation.
In accordance with an advantageous feature of the present invention, the operating program for in-circuit emulation is not stored in the internal ROM memory, but in an external, and therefore easily accessible memory. The connecting device can be used to operate the microcontroller in a plurality of operating modes, with the result that the same circuit design can be used both for the standard commercially manufactured product and for its emulation variant. The additional circuit outlay essentially comprises suitable changeover switches for the connecting ports of the microcontroller, and is kept within acceptable bounds.
The arrangement, according to the invention, for in-circuit emulation comprises two identical microcontrollers, which are operated as master and slave, as well as the external program memory. The slave receives the same program instructions parallel to the master. The connection ports, which are differently occupied in the master by comparison with normal operation, are handled by the slave and transmitted to the master. The operating program is processed in the master. The occupation of the external connecting port of the overall circuit comprising master, slave and external memory, corresponds to the normal operation of the standard commercially manufactured microcontroller. When the standard commercially manufactured microcontroller is present, in-circuit emulation is also already possible. It is advantageous that all design changes carried out in the standard commercially manufactured product (for example time response of connecting ports and switching edges, live currents, etc.) are also directly available in the emulator.
It is accordingly an object of the invention to provide a circuit arrangement for in-circuit emulation, comprising a first and a second identical microcontroller (
2
,
3
), which in each case have at least five external connections (P
0
, . . . , P
4
; P
0
′, . . . , P
4
′) as well as a connecting device (
9
,
9
′), which serves to connect the connections inside the microcontroller to one another and to the internal function units (
7
,
7
′) of the microcontroller, and has a different setting in the first and second microcontrollers (
2
,
3
), and comprising a memory (
4
) for an operating program with data and address connections (D, AL, AH), the identical connections of the two microcontrollers not being connected to one another, the data and address connections (D, AH, AL) of the memory (
4
) being connected in each case to one of the connections (P
0
, P
2
) of the first microcontroller (
2
) and the data connection (D) of the memory (
4
) being connected to one of the connections (P
1
) of the second microcontroller (
3
), the microcontrollers being mutually connected to one another via one connection (P
3
, P′) in each case, and the remaining connections (P
1
, P
4
; P
0
′, P
2
′, P
3
′) of the microcontrollers being provided for connection to an application system, and the connecting devices (
9
,
9
′) being set in such a way that the function units (
7
) of the first microcontroller (
2
) are provided with the operating program from the memory (
4
), and the signal traffic at the remaining connections (P
0
′, P
2
′, P
3
′) of the second microcontroller (
3
) being provided via the terminal (P
3
) for connection to the second microcontroller (
3
).
In accordance with an added feature of the invention, the internal function units (
7
,
7
′) of the first and second microcontrollers (
2
,
3
) in each case have an internal address connection (ah) and an internal data connection (al/d) for calling the operating program as well as five internal connections (p
0
, . . . , p
4
), wherein the internal address connection (ah) and the internal data connection (al/d) are connected to a first and a second external connection (P
0
, P
2
) inside the first microcontroller (
2
) via a connecting device (
9
) thereof in a first setting, first, second and third internal connections (p
0
, p
2
, p
3
) are connected to a third external connection (P
3
), and fourth and fifth internal connections (p
4
, p
1
) are connected to a fourth and fifth external connection (P
4
, P
1
), and wherein the internal data connection (al/d) is connected to the fifth external connection (P
1
′) inside the second microcontroller (
2
) via connecting device (
9
′) thereof in a second setting, and the first, second and third external connections (P
0
′, P
2
′, P
3
′) are connected to the fourth external connection (P
4
′).
In accordance with an additional feature of the invention, concerning the first microcontroller (
2
) the second external connection (P
2
) is connected to the address connection (AH, AL) of the external memory (
4
), and the first external connection (P
0
) is connected to the data connection (D) of the external memory (
4
), and wherein concerning the second microcontroller (
3
) the fifth external connection (P
1
′) is connected to the data connection (D) of the external memory (
4
), and the fourth external connection (P
4
′) is connected to the third external connection (P
3
) of the first microcontroller.
In accordance with an another feature of the invention, a clock synchronizes the two microcontrollers (
2
,
3
).
In accordance with a further added feature of the invention, each of the external and internal connections (P
0
, . . . , P
4
, P
0
′, . . . , P
4
′, p
0
, . . . , p
4
) comprises a multiplicity of individual signal lines.
In accordance with a further additional feature of the invention, the internal data connection (al/d) of the internal function units (
7
,
7
′) is constructed in order to receive or transmit data and a portion of the address of the memory (
4
) in a time-division multiplexed fashion, and the internal address connection (ah) of the internal function units (
7
,
7
′) is constructed in order to transmit another portion of the address of the memory (
4
).
In accordance with yet another feature of the invention, there is provided in each case on the microcontrollers (
2
,
3
) at least one further external connection (P
5
, P
6
, . . . , P
5
′, P
6
′, . . . ) which is connected in each case to a means for generating a constant signal level, wherein the microcontrollers (
2
,
3
) in each case have circuit means which can be used to interrogate the signal level present during a reset operation, and

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