Circuit arrangement for geometric image transformation including

Details Circuit arrangement for geometric image transformation including Circuit arrangement for geometric image transformation including

1992-06-16

1994-06-07

Harkcom, Gary V.

Boots, shoes, and leggings

395125, 395133, 395136, 395162, 395164, 36441313, G06F 1562

Patent

active

053197496

ABSTRACT:
A memory arrangement for fast geometric transformation of an image is formed by a first memory for storing image values generated by an image-generating system, a second memory for storing image values corresponding to an image resulting from geometric transformation of image values from the first memory, and a third memory with the same number of memory addresses as the second memory and in which an assignment between the addresses of the first and second memories is stored.

REFERENCES:
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patent: 4833625 (1989-05-01), Fisher et al.
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patent: 4870692 (1989-09-01), Zuiderveld et al.
patent: 4965726 (1990-10-01), Heuscher et al.
"Variable Core-Size Linear Transformation Program", IBM Technical Disclosure Bulletin, vol. 14, No. 10, Mar. 1972.

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