Circuit arrangement for generating two signals staggered in time

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input

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327237, 327243, 327295, 326 52, H03H 1116

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active

059735325

ABSTRACT:
The circuit arrangement for generating two signals staggered in time from a clock signal and for measuring their time stagger receives at its input a clock signal, from which it generates an undelayed signal and a signal delayed relative to the undelayed signal. The generated signals appear at a first and second output of the circuit arrangement, respectively. A delay time measuring arrangement comprises a reversible inverter connected between the input of the circuit arrangement and the first output of the circuit arrangement and a NAND gate. The NAND gate receives at one input the delayed signal and at the other input the output signal of the inverter and furnishes an output signal from which the time stagger existing between the undelayed signal and the delayed signal can be precisely determined. The reversible inverter is switchable by a switching signal between a non-inverting condition in a working phase and an inverting condition in a measuring phase. The reversible inverter may by formed by an XOR gate receiving at one input the clock signal and at the other input the switching signal.

REFERENCES:
patent: 3950705 (1976-04-01), Fuerherm
patent: 4031410 (1977-06-01), Kikuchi
patent: 4128812 (1978-12-01), Pavlis
patent: 4845728 (1989-07-01), Truong et al.
patent: 5028824 (1991-07-01), Young
patent: 5544203 (1996-08-01), Casasanta et al.

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