Circuit arrangement for generating synchronization signals in a

Details Circuit arrangement for generating synchronization signals in a Circuit arrangement for generating synchronization signals in a

1991-07-16

1993-08-10

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370106, H04J 306

Patent

active

052355969

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The invention is directed to a circuit arrangement for generating synchronization signals in a transmission of data from a transmission unit to a reception unit, whereby the data are transmitted by binarily coded data signals that are sampled by reception clocks for the recovery of the transmitted data and whereby the reception clocks are synchronized phase-wise by synchronization signals allocated to the data signals upon employment of a counter that is respectively counted from an initial value up to a final value by clock pulses whose repetition rate is significantly higher than the repetition rates of the data signals.
It is notoriously known to transmit data with binary data signals from a transmission unit to a reception unit without accompanying clock pulses. In such a transmission, a clock control is provided in the reception unit, this clock control generating reception clocks from the received data signals and supplying them to a sampling unit. The reception clocks therein sample the data signals and recover the transmitted data from the data signals. To this end, the data signals should be respectively sampled in their middle insofar as possible.
Such a reception unit of the prior art is shown in FIG. 1 in the form of a block circuit diagram and its functioning shall be explained in greater detail together with the time diagrams shown in FIG. 2, the time t being shown therein in abscissa direction and the momentary values of signals being shown therein in ordinate direction.
Given the reception unit shown as a block circuit diagram in FIG. 1, the binarily coded data signals D are supplied, first, to a pulse generator IG and, second, to the sampling unit AB that recovers the transmitted data from the data signals D upon employment of reception clock ET and makes them available for a further processing as received data ED. The reception clock ET is generated in a clock control TS. For synchronizing the reception clock ET with the data signals D, the pulse generator IG generates synchronization signals SY. These synchronization signals SY are adjacent at the clock control TS and the latter sets the phase relation of the reception clock ET such that the reception clock ET always samples the data signals D in its middles insofar as possible.
The data signals D shown in FIG. 2 are undistorted data signals, i.e. they change their binary values at whole multiples of prescribed time intervals. At points in time at the trailing edges of the data signals D that respectively correspond to one another, the pulse generator IG generates the synchronization signals SY with which the phase relation of the reception clock ET generated in the clock control TS is set such that the data signals D are sampled in its middles at times t1 through t5 by the leading edges of the reception clock ET in order to recover the received data ED.
The data signals can be subject to distortions in the transmission of the data, for example via a radio link affected with interference. When the reception clocks are derived from these data signals, the data signals cannot be reliably sampled since the reception clocks are only synchronized by the edges of the data signals.


SUMMARY OF THE INVENTION

It is therefore the object of the invention to specify a circuit arrangement for generating synchronization signals, the data signals also being sampled with great reliability given the employment thereof even when they are subject to distortions.
In a circuit arrangement of the species initially cited, this object is inventively achieved by the circuit arrangement wherein: the counter can be respectively counted from a constant initial value up to a constant final value; a synchronization unit is provided at which the data signals are received generating a load signal given every change of the binary value of the data signals from a first binary value to a second binary value, the load signal setting the counter to its initial value and generating switch-over signals at every change of the binary values of the

REFERENCES:
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patent: 3983498 (1976-09-01), Malek
patent: 4031316 (1977-06-01), Reisinger et al.
patent: 4517681 (1985-05-01), Mantellina et al.
patent: 4771441 (1988-09-01), Spengler et al.
patent: 5042053 (1991-08-01), Hoppes
patent: 5052026 (1991-09-01), Walley

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