Circuit arrangement for generating an n-bit output pointer,...

Details Circuit arrangement for generating an n-bit output pointer,... Circuit arrangement for generating an n-bit output pointer,...

2008-09-23

2008-09-23

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S236000, C365S230060

Reexamination Certificate

active

11593234

ABSTRACT:
A circuit arrangement for generating an n-bit output pointer in a semiconductor memory comprises at least one m-bit interface for accepting an m-bit reference signal, at least one m-bit binary counter, a decoder arrangement connected downstream of the binary counter, and outputs for providing the bits of the output pointer. The reference signal comprises an information regarding a read latency to be adjusted utilizing the output pointer, the at least one counter provides an m-bit counter reading signal comprising a current counter reading, and the decoder arrangement comprises a plurality of decoder devices each comparing the current counter reading signal with a reference value which is associated with a respective of the decoder devices. Each decoder device provides one bit of the output pointer on the basis of the comparing.

REFERENCES:
patent: 5655113 (1997-08-01), Leung et al.
patent: 6215837 (2001-04-01), Yi
patent: 6959016 (2005-10-01), Keeth et al.

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