Electricity: motive power systems – Automatic and/or with time-delay means – Speed or rate-of-movement
Patent
1987-07-06
1989-04-18
Ro, Bentsu
Electricity: motive power systems
Automatic and/or with time-delay means
Speed or rate-of-movement
307519, 324 78J, 328140, G01R 2309
Patent
active
048230600
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to a circuit arrangement for generating a useful direct voltage signal associated with the frequency of an alternating current signal, particularly for regulating the synchronism of an electric motor, the arrangement including a comparator circuit which converts two opposite polarity halfwaves of the alternating current signal into pulses whose edges trigger a measuring and control circuit which is able to generate direct voltages corresponding to the half-period durations of the alternating current signal measured from the respective zero passages.
Numerous circuits are known for converting the frequency of a sinusoidal signal voltage into a direct voltage that is proportional to that frequency. Frequently, the sample-and-hold principle is employed to furnish a frequency proportional direct voltage which has a sufficiently low residual ripple. After each trigger signal, a time proportional voltage is transmitted in bursts to a storage capacitor to replace the preceding measurement value. If only the ascending or descending zero passage of the signal voltage is selected as the trigger signal, it is possible to realize high repetition accuracy but only one trigger signal is obtained per full sinusoidal oscillation. However, trigger circuits are known already which furnish a trigger signal during each zero passage before or after the conversion of the sinusoidal voltage into a rectangular voltage (frequency doubling). These circuits are useful up to a certain accuracy. If, however, one desires to perform very precise angular velocity measurements, for example, to ensure or measure synchronism of a motor, two error sources must be compensated, one being caused by the offset voltage of the comparator and the other by periodic system specific harmonics in the tachogenerator.
SUMMARY OF THE INVENTION
Based on this state of the art, it is the object of the invention to provide a circuit arrangement of the above-mentioned type which is distinguished by high measuring accuracy, with the time delay caused by the effected frequency demodulation and by the filters as well as the residual ripple in the direct voltage remaining very low.
This is accomplished, according to the invention, in that the comparison voltage input of the comparator is connected with the output of a difference switching circuit, whose two inputs are each connected to a voltage store which is connectable with the useful direct voltage signal by way of associated first and second switches, with the first switch being used to periodically couple out the useful direct voltage signal associated with the first half-periods and the second switch being used to periodically couple out the useful direct voltage signal associated with the second half-periods.
Due to the fact that the useful direct voltage signal can be coupled out via the first and second switches, each time in association with the half-periods, it is possible to effect a regulation which ensures that the detected half-periods or half waves on the average have the same length over a period of time which is long compared to the period duration. In particular, this reliably and securely compensates for drifting of the comparator offset voltage which would otherwise lead to inaccuracies in the measurements. The voltage stores may be realized in a simple manner by means of storage capacitors. In a suitable embodiment, the difference switching circuit is configured as a differential amplifier, with the regulating circuit then exhibiting PI behavior.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block circuit diagram for the circuit arrangement according to the invention;
FIG. 2 is a block circuit diagram according to FIG. 1 including a detailed illustration of the measuring and control circuit for time measurement and control; and
FIG. 3 is a block circuit diagram of a microprocessor controlled circuit arrangement according to the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 shows the schematically illustrated tacho shaft
REFERENCES:
patent: 3798529 (1974-03-01), Jones
patent: 4480217 (1984-10-01), Robbins et al.
patent: 4488096 (1984-12-01), Cap et al.
patent: 4498036 (1985-02-01), Saleurka
patent: 4769611 (1988-09-01), Frierdich
Papst-Motoren GmbH & Co. KG
Ro Bentsu
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