Circuit arrangement for generating a digital clock signal

Details Circuit arrangement for generating a digital clock signal Circuit arrangement for generating a digital clock signal

2006-06-13

2006-06-13

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S101000, C327S115000, C327S291000

Reexamination Certificate

active

07061296

ABSTRACT:
A circuit arrangement for generating a digital clock signal which manages without a crystal oscillator and has a low current consumption. The circuit arrangement includes: a transistor circuit having a first, n-channel FET transistor and a second, p-channel FET transistor, which are connected in series, a comparator having a positive comparator input, a negative comparator input and a comparator output, a device for providing two switching thresholds to the negative input of the comparator, and a capacitance, which is alternately charged and discharged via the two FET transistors. The voltage present at the capacitance is fed to the positive comparator input, and the output voltage of the comparator, which represents a digital clock signal, is fed back to the input of the device for providing two switching thresholds and to the gate terminals of the first and second FET transistors.

REFERENCES:
patent: 4535305 (1985-08-01), Matsuo et al.
patent: 4603308 (1986-07-01), Briefer
patent: 4983931 (1991-01-01), Nakano
patent: 5534819 (1996-07-01), Gunter et al.
patent: 6020792 (2000-02-01), Nolan et al.
patent: 6052035 (2000-04-01), Nolan et al.
patent: 6069536 (2000-05-01), Oh
patent: 6356161 (2002-03-01), Nolan et al.
patent: 6741114 (2004-05-01), Kim
patent: 6873216 (2005-03-01), Seya
patent: 2001/0026182 (2001-10-01), Brox
patent: 2002/0044001 (2002-04-01), Matsui
patent: 2002/0167348 (2002-11-01), Kim
patent: 0 293 045 (1988-11-01), None

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