Circuit arrangement for generating a clock-pulse signal...

Details Circuit arrangement for generating a clock-pulse signal... Circuit arrangement for generating a clock-pulse signal...

2002-03-27

2003-05-06

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S147000

Reexamination Certificate

active

06559696

ABSTRACT:

CLAIM FOR PRIORITY
This application claims priority to International Application No. PCT/DE00/03219 which was published in the German language on Sept. 15, 2000.
TECHINCAL FIELD OF INVENTION
The invention relates to a circuit having a clock signal with a frequency synchronous with a reference clock signal.
BACKGROUND OF THE INVENTION
In digital communications systems, individual communications system components require an accurate system clock for synchronizing interchange of communications data. Normally, highly accurate reference clock signals are supplied to individual communications system components for this purpose, e.g. via the public network. Generally, the reference clock signals supplied do not directly provide clock control for a communications system component, but rather are routed to a phase locked loop in which system clock signals are formed and transmitted to individual assemblies.
Since interference-free transmission of an external reference clock signal cannot be guaranteed at all times, a communications system component is often provided with a dedicated highly stable reference clock source which, in the event of the external reference clock signal disappearing, is used to stabilize the clock generator via a second phase locked loop.
Such a circuit arrangement is known from European patent application 0 262 481, for example. This circuit arrangement contains a reference reception part which receives the external reference clock signals and is connected to a first input of a first phase comparison device. The output of the first phase comparison device is routed via an integration device and a filter whose output can be connected to a downstream voltage controlled oscillator using a switching element. The synchronous-frequency clock signals formed in the voltage controlled oscillator are routed from the latter's output both to an output of the circuit arrangement and to a second input of the first phase comparison device.
The known circuit arrangement also contains a highly stable reference clock source whose output is connected to a first input of a second phase comparison device. The second input of this second phase comparison device is likewise connected to the output of the voltage controlled oscillator. The output of the second phase comparison device can be connected either to an additional filter or to a minuend input of a subtraction element using a further switching element. The output of the subtraction element, to whose subtrahend input the output of the additional filter is connected, is connected to another input of the switching element via a further filter.
The known circuit arrangement thus contains two phase locked loops, the first phase locked loop being controlled by the external reference clock signals, and the second phase locked loop being controlled by the reference clock signals from the highly stable reference clock source. Normally, the voltage controlled oscillator is synchronized with the supplied external reference clock signals. If the external reference clock signals disappear or if prescribed phase differences are exceeded, there is a switch to the highly stable reference clock source. In the additional filter, during synchronization by the external reference clock signals, the discrepancies between the synchronous-frequency clock signals and the reference clock signals from the highly stable reference clock source are gathered and correction adjustment information is formed. After switching to the highly stable reference clock source, the subtraction element is used to include this correction adjustment information in the formation of adjustment information for the voltage controlled oscillator.
However, this circuit arrangement has the problem that, to avoid an excessively long regulation delay, the frequency of the highly stable reference clock source should be comparatively high. A high clock frequency also results in a comparatively high current consumption, however, which means that such a circuit arrangement is not very suitable for battery operation. In addition, such a circuit arrangement is provided with switching means in order to detect cyclically occurring phase overflows in the second phase comparison device. In this context, phase overflow denotes when a phase difference of 360 degrees is exceeded. Such phase overflows occur cyclically if the frequency of the reference clock source and the frequency of the voltage controlled oscillator, synchronized with the external reference clock signal, differ from one another systematically, possibly after they have each passed through a frequency divider.
SUMMARY OF THE INVENTION
In one embodiment of the invention, there is a circuit arrangement for producing a clock signal whose frequency is synchronous with that of reference clock signals which has an improved regulation characteristic, in particular when a reference clock signal having a comparatively low clock frequency is supplied.
The circuit arrangement includes, for example, an oscillator whose clock frequency, in a first operating mode of the circuit arrangement, synchronized with a supplied, first reference clock signal using a first phase locked loop which comprises a first phase comparison device. In addition, a phase control element and a second phase comparison device are provided which are used in the first operating mode to detect a discrepancy between a supplied, second reference clock signal and the synchronous-frequency clock signal from the oscillator and to form phase correction information. In a second operating mode of the circuit arrangement, e.g. if the first reference clock signal disappears, the oscillator is no longer synchronized using the first reference clock signal, but rather using the second reference clock signal. Such a second operating mode is often also referred to as “hold-over mode”. In this case, the phase correction information formed in the first operating mode is brought into the phase control. This is done by virtue of a phase control element inserting or removing clock phases in the clock signal from the oscillator on the basis of the phase correction information before phase comparison with the second reference clock signal.
Correction of the oscillator phase or oscillator frequency before phase comparison with the second reference clock signal makes it easy to prevent cyclically occurring phase overflows during phase comparison when there is a systematic discrepancy between the oscillator clock signal, whose frequency is synchronous with that of the first reference clock signal, and the second reference clock signal.
One advantage of the circuit arrangement provides very good regulation characteristic and short regulation time constants which are ensured, in particular, even for a comparatively low-frequency second reference clock signal. The production of low-frequency reference clock signals generally requires less power than the production of higher-frequency reference clock signals, which means that the circuit arrangement in conjunction with a low-frequency reference clock generator is also well suited to battery operation. The good regulation characteristic is a consequence of the phase correction by the phase control element being applied to the clock signal from the oscillator. Since the clock signal from the oscillator normally has a much higher frequency than the second reference clock signal, removal or insertion of individual clock phases in the clock signal from the oscillator makes it possible to control the frequency of this clock signal very precisely before phase comparison. In particular, this causes only very low phase and pulse jitter.
Another advantage of the inventive circuit arrangement is that no processor is required for implementing it. Instead, the circuit arrangement can be implemented using an inexpensive ASIC chip (Application Specific Integrated Circuit), for example.
In one aspct of the invention, the output of the first phase comparison device can be connected to the frequency control input of the oscillator via a switching element, suc

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