Circuit arrangement for gating out pulses and/or pulse gaps whos

Details Circuit arrangement for gating out pulses and/or pulse gaps whos Circuit arrangement for gating out pulses and/or pulse gaps whos

1975-03-28

1976-12-14

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

328111, 328119, 328130, 329106, H03K 513

Patent

active

039977986

ABSTRACT:
A novel circuit arrangement is provided for gating out pulses and/or pulse gaps whose duration is shorter than a given test period t.sub.p from a sequence of digital pulses present at the input end. The arrangement is such that the test period can be set with arbitrary accuracy and yet at the same time can be arbitrarily varied. It is insensitive to temperature fluctuations within wide limits.
A principal feature of the present invention is to provide a circuit arrangement in which at least one counter is provided which may be set and which exhibits a setting input for the setting of a fixed or variable initial value in the counter, and in which the test period t.sub.p may be determined as a counter period from the initial value after a give value in the counter.
If only pulses are to be gated out, such a circuit arrangement is advantageously constructed in such a manner that at least one gate is provided which has at least two inputs, and at least one decoder is provided having at least first inputs for the parallel input of at least one digital word and having one output, and at least one binary storage element (flip-flop circuit) is provided having at least two inputs, where the output of the gate is connected to the counter input of the counter, the counter outputs for the parallel withdrawal of the count are connected to the first inputs of the decoder and the output of the decoder is connected to a first input of the binary storage element, and where a first input of the gate is connected to the setting input of the counter and to a second input of the binary storage element.
If only pulse gaps are to be gated out, advantageously in this circuit arrangement the gate is preceded by an inverter whose output is connected to the first input of the gate.

REFERENCES:
patent: 3646371 (1972-02-01), Flad
patent: 3667054 (1972-05-01), Nelson
patent: 3753135 (1973-08-01), Kastner et al.

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