Circuit arrangement for frequency multiplication

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377 57, G06F 752

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active

058222294

ABSTRACT:
A circuit arrangement for frequency multiplication is described, by means of which a digital output signal is produced, the pulse repetition rate of which is obtained from one of the output signals by multiplication by an adjustable factor K. A high accuracy of the frequency of the output signal is obtained by the fact that an input counter is clocked by a digitally controlled oscillator and by the fact that the following means for controlling an output counter are provided:

REFERENCES:
patent: 4017719 (1977-04-01), Kaplan et al.
patent: 4071743 (1978-01-01), Upton
patent: 4086471 (1978-04-01), Takahashi
patent: 4112492 (1978-09-01), Summers
patent: 4242639 (1980-12-01), Boone
patent: 4328484 (1982-05-01), Denecke
patent: 4339722 (1982-07-01), Sydor et al.
patent: 4669099 (1987-05-01), Zinn
patent: 4773031 (1988-09-01), Tobin
patent: 4941160 (1990-07-01), Sheahan
"Frequenzsynthese MIT Numerisch Gesteuerten Oszillatoren" A. Rupp, Elektronic, 14, (1990) pp. 81-88.

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