Boots – shoes – and leggings
Patent
1981-09-15
1984-12-04
Thomas, James D.
Boots, shoes, and leggings
G06F 1300
Patent
active
044868251
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
This invention relates to a microprocessor system comprising a microprocessor forming a central processor unit which is provided with control outputs for memory read, memory write, peripheral device read and peripheral device write, comprising furthermore a memory and a peripheral device provided with read and write control inputs connected to the microprocessor via a data bus, an address bus and a control bus.
BACKGROUND OF THE INVENTION
A microprocessor system of the above type is described for example in the INTEL 8080 Microcomputer Systems User's Manual, Volume 9, 1975 [see FIGS. 3-9 in pages 3-8].
In this system, the memory read and memory write, peripheral device read and peripheral device write outputs of the microprocessor are connected to the corresponding read and write inputs of the memory elements and peripheral devices. The microprocessor controls the peripheral devices by means of peripheral device handler instructions created especially for this purpose. This solution is disadvantageous in the respect that in the system the peripheral devices performing the same function but having necessarily different addresses can not be addressed and handled with a single program--hence a peripheral device handler instruction may refer only to a single peripheral device address--, consequently these programs should be multiplicated. A further disadvantage is that by means of the peripheral device handler instructions the data are accessible only through a special register, i.e. the so called accumulator register of the microprocessor.
In the abovementioned publication, the authors attempted to eliminate this disadvantage by using a system shown in FIGS. 3-10 in pages 3-9. In this solution, the peripheral devices are selected via the memory read and memory write outputs gated with the most significant bit of the address bus, rather than via the peripheral device read and write outputs of the microprocessor. In this way, the peripheral devices can be addressed in the system as memory cells, and in the program the peripheral devices should be handled with references to these memory cell addresses. This solution has the disadvantage, on one hand that memory reference instructions having longer execution time and greater memory area requirement should be used, even when it would be unnecessary, for example when peripheral devices are to be handled which are unique in the system concerning their types. A further disadvantage lies, on the other hand, in that, in this case, the peripheral device handler instructions of the microprocessor can not be used at all, therefore the programs containing such types of instructions--which programs are developed up to now in a great number--can not be used without modifications. These disadvantages restrict to a great extent the usability of such systems, limit their application areas.
The aim of the present invention is to eliminate these disadvantages.
The object of the present invention is to provide a microprocessor system in which the memory requirement and run time of the programs are minimal, and which at the same time allows the execution of programs made for known systems without modifications.
SUMMARY OF THE INVENTION
According to the present invention, a microprocessor system comprises a microprocessor forming the central processor unit provided with memory read and memory write control outputs and peripheral device read and peripheral device write control outputs, comprises furthermore a peripheral device and a memory connected to the microprocessor via data-, address- and control buses and provided with read and write control inputs; said microprocessor system comprises a combination logic circuit provided with a first, second, third, fourth and fifth inputs and a first and second outputs; the memory read control output of the microprocessor is connected with the second input of the first combination logic circuit and with the read control input of said memory, the memory write control output of the microprocessor is connected with
REFERENCES:
patent: 3939455 (1976-02-01), Toyosawa
patent: 3943495 (1976-03-01), Garlic
patent: 4112490 (1978-09-01), Pohlman et al.
"Kiloband Microcomputing", Mar. 1979, pp. 108-112.
"Intel MCS-80/85 Family User's Manual", Oct. 1979, pp. 6-115 to 6-131.
Adonyi Ivan
Farkas Endre
Hegedus Gyula
Kormendy Attila
Mogyorosi Istvanne
Clark David L.
Telefongyar
Thomas James D.
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