Circuit arrangement for evaluating a video synchronizing signal

Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry

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358148, 358150, 358154, H04N 504

Patent

active

049223445

ABSTRACT:
A circuit arrangement for evaluating a video synchronizing signal formed by line synchronizing pulses whose regular sequence between two fields is interrupted by a field synchronizing pulse and the time interval between the edges of a field synchronizing signal and the edges of a subsequent first line synchronizing pulse is characteristic of each field. In the circuit arrangement the evaluation of the video synchronizing signal is based on a field synchronizing pulse and the line synchronizing pulses subsequent thereto. This evaluation is effected by a detector, which detects the field synchronizing pulses in the video synchronizing signal. The circuit arrangement, a first logic circuit which is connected to the output of the detector and which the operation of a first counter clocked by an oscillator is controlled, two decoders connected to the counting stages of the first counter and supplying an output pulse, as long as the counter position cycles throug a predetermined counting range for each decoder, and a second logic circuit connected to the decoders. Also the video synchronizing signal is applied to this logic circuit. From their output variables it cna be recognized whether one of the two decoders and which one of the two decoders has supplied an output pulse during a pulse in the video synchronizing signal.

REFERENCES:
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patent: 3531593 (1970-09-01), Bell
patent: 4414570 (1983-11-01), Braune et al.
patent: 4459612 (1984-07-01), Shinkai et al.
patent: 4683495 (1987-07-01), Brock
patent: 4701799 (1987-10-01), Yoshimura
patent: 4827341 (1989-05-01), Akimoto et al.

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