Circuit arrangement for driving a load by two transistors

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver

Reexamination Certificate

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C327S110000, C327S423000

Reexamination Certificate

active

06337587

ABSTRACT:

The present invention relates to a circuit arrangement comprising two transistors connected in series with a driven load.
FIELD OF THE INVENTION
Numerous technical uses exist for circuit arrangements designed to drive, through two driver transistors, a load connected in series with these transistors. A typical example of load driven by such an output stage consists in the electric ignition element of the gas generator for the airbag of a motor vehicle. In this example, a defined minimum power for igniting the electric ignition element is converted therein for a short time. The energy supply in this case is largely provided by an energy store comprising e.g. a capacitor. For protection of the driver transistors but also for safeguarding that no excessive current will flow through the load, an output stage is designed to be current-limiting, which is realized by use of transistors with current-limitation.
FIG. 1
illustrates a known circuit arrangement with current-limitation. In such a current-limiting output stage, a general problem consists in that the distribution of the electric loss power among the two transistors M
1
and M
2
is nonuniform and thus disadvantageous.
In the known circuit arrangement according to
FIG. 1
, a load R, which can be resistive, capacitive or inductive, is powered by the two transistors M
1
and M
2
which can be provided as bipolar or field effect transistors. Since the load may be arranged far away from the two transistors M
1
and M
2
, a short-circuit fuse is required for the two transistors M
1
and M
2
so as to avoid damage during operation or assembly. Otherwise, short-circuits of the supply lines with the potentials U
1
and U
2
towards a positive or negative supply would cause damage to the transistors M
1
and M
2
respectively.
Further, limiting the current can be required for the load R. Thus, for instance, it should be prevented that overcurrents are flowing at the beginning or the end of an on-state. Further, an avoidance of such overcurrents may be advisable because the energy store feeding the circuit arrangement will discharge too quickly. This should be prevented e.g. when using the inventive circuit arrangement in motor vehicles to ignite the ignition elements of the gas generators of a plurality of airbags. Notably, to safeguard the triggering of all airbags even after breakdown of the motor vehicle's network, none of the ignition elements must receive a current larger than the ignition current because the energy in the energy store would otherwise not be sufficient for igniting all of the required airbags.
As already briefly indicated above, the current-limitation in the transistors M
1
and M
2
is performed in the manner known per se by means of shunt resistors or by measuring the voltage drop across the transistors or part of the transistors. In this regard, it is physically impossible to achieve the same voltage drop and thus the same power across both of the transistors. This is because the transistors, due to manufacturing tolerances, have different limiting currents. As a result, the limitation will always have a stronger effect on one of the two transistors M
1
and M
2
than on the respective other one. Thus, a very large voltage drop will take place across one of the two transistors M
1
,M
2
so that the largest part of the power has to be consumed by this transistor. In the circuit arrangement according to
FIG. 1
, it is assumed that the current-limitation across transistor M
2
is slightly smaller than across transistor M
1
; in other words, I
lim(M1)
is larger than I
lim(M2)
.
If it is further assumed that the on-state resistances of the transistors M
1
and M
2
in the fully driven state are smaller than the resistance of the load R and that the current obtained by the series connection is larger than the current-limitation on one of the two transistors M
1
,M
2
, a very large voltage drop U
2
across transistor M
2
and thus a very large power consumption by the transistors M
2
will occur during operation. The transistor T
1
will remain in the fully driven state, and due to the small voltage drop across this transistor, only little power will be consumed. The rest of the power is consumed by the load R. The large power consumption in the transistor T
2
may lead to considerable heat-up and eventually cause damage to this transistor. Generally, at least a strong oversizing of the power consumption capability of the transistor M
2
will be required. This in turn has an adverse effect on the area requirement of the transistor, considering that the instant circuit arrangement on the whole is provided as an IC circuit.
Another approach to prevent a non-uniform distribution of the loss powers in the two transistors M
1
and M
2
or to reduce the effect thereof resides in that the two transistors M
1
,M
2
are coupled to each other such that, upon detection of the current-limitation on the transistor M
2
, the transistor M
1
can be influenced by a suitable technique from the field of circuit engineering, e.g. by briefly reducing the current-limitation of the transistor Ml. Such an approach would cause the two transistors M
1
,M
2
to alternately run into the current-limiting range, which in turn would result in undesirable current oscillation phenomena. Besides, it is in numerous applications undesired and, due to large distances, partially hardly even possible to additionally couple the transistors M
1
,M
2
with each other for controlling the current-limitation of one transistor in dependence on the response of the current-limitation of the other transistor.
Known from DE-A-15 13 168 is an output stage for driving a load wherein two serially connected transistors are in turn connected in series with the load which is to be driven. One of the two transistors is controlled to have the current on its conductive path limited to a maximum value.
It is an object of the invention to provide a circuit arrangement, designed for driving a load by two transistors connected in series, which makes it possible to distribute the loss power onto both transistors in a simple manner.
SUMMARY OF THE INVENTION
In the circuit arrangement according to the invention, the two transistors have their control inputs respectively connected to current-limiting circuits which have the effect that the currents flowing via the conductive paths of the transistors are limited to first and second maximum values, respectively. The current-limiting value of the first transistor is larger than the current-limiting value of the second transistor. This, as already mentioned above in the description of the circuit arrangement known from the state of the art, is actually the normal case, as caused by manufacturing tolerances of the transistors. This normal case is deliberately utilized by the invention in that, with the second transistor subjected to voltage limitation, the voltage drop across the first transistor is increased so that a part of the power which otherwise would have been consumed by the second transistor is transmitted to the first transistor. Notably, according to the invention, if a current of the amount of the second maximum value is flowing, the control signal at the control input of the first transistor can be set in such a manner that a voltage is caused to drop on the conductive path of the first transistor which is larger than that voltage which would drop if a current of the amount of the second maximum value were flowing via the conductive path of the first transistor.
The influencing of the control signal at the control input of the first transistor can be realized simply through feedback of the voltage drop across the first transistor. Thus, the inventive circuit arrangement obviates the need for a coupling and an additional connecting of the current-limiting circuits of both transistors, so that, with lowest expenditure, the loss power to be handled in the two transistors is distributed in a more evenly, thus preventing that one of the two transistors hap to take up a substantially higher loss power than the other on

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