Circuit arrangement for digital multiplication of integers

Details Circuit arrangement for digital multiplication of integers Circuit arrangement for digital multiplication of integers

1996-01-18

1999-09-21

Elmore, Reba I.

Boots, shoes, and leggings

G06F 752

Patent

active

059562641

ABSTRACT:
A circuit arrangement for digital multiplication of integers, having an encoding unit, an adding unit, which adds the output values of the encoding unit, and a decoding unit, which decodes the output value of the adding unit. The encoding unit encodes the numbers according to the following formula:

REFERENCES:
patent: 4031377 (1977-06-01), Deutsch et al.
patent: 4366549 (1982-12-01), Katayama
patent: 4555768 (1985-11-01), Lewis, Jr. et al.
patent: 4682302 (1987-07-01), Williams
patent: 4720809 (1988-01-01), Taylor
patent: 4852038 (1989-07-01), Wagner et al.

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