Circuit arrangement for detection of an erroneous selection sign

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371 572, 371 52, G06F 1100

Patent

active

052672506

ABSTRACT:
An erroneous selection signal detecting circuit in a data transfer system. Conventional error detecting systems may not be capable of detecting errors in the selection signal generating circuit using available parity of checksum procedures. The selector means in the present invention selects one of a plurality of input signals on the basis of selection information. This information is applied both to appropriate selection circuits and to two additional selecting circuits also continually receiving fixed data input values. The outputs from these additional circuits are compared to the selection signals through EXCLUSIVE-OR gates, a particular logical indication from the EXCLUSIVE-OR gates indicating a malfunction.

REFERENCES:
patent: 3610842 (1971-10-01), Formenti et al.
patent: 4020460 (1977-04-01), Jones et al.
patent: 4380813 (1983-04-01), Fogell et al.
patent: 4945540 (1990-07-01), Kaneko
patent: 4949343 (1990-08-01), Kaneko

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