Circuit arrangement for designational reading of information of

Details Circuit arrangement for designational reading of information of Circuit arrangement for designational reading of information of

1988-07-13

1990-02-27

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370112, H04J 302

Patent

active

049052365

ABSTRACT:
The reading times for a designational reading of information communicated via an ISDN-oriented interface are formed for a recording device and transmitted thereto with the assistance of a circuit arrangement, being formed from bit clock signals and bit group clock signals, which define the boundaries of the bit groups comprising 32 bits, that are present in an ISDN-oriented interface. The reading times present in the form of bit clock pulses inform the recording device of the times at which the information are to be read and subsequently stored. The circuit arrangement contains a shift register that is formed by a plurality of registers corresponding in number to the plurality of bits of a bit group, a reset device that is realized, for example, by an inverter and a switch, and also contains an AND gate and a plurality of switch devices whose setting determines which information are, respectively, bits of a bit group are to be read and stored.

REFERENCES:
patent: 4797654 (1989-01-01), Young et al.
patent: 4821264 (1989-04-01), Kim
Telcom Report 9 (1986) No. 4 pp. 230 to 234; "VLSI Chips for Basic Access in the IOM-Architecture".

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