Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Patent
1993-12-14
1996-09-10
Nelms, David C.
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
327279, 327291, 327293, 327294, 327400, 327401, H03H 1126, H03K 104, H03K 1728
Patent
active
055549497
ABSTRACT:
A circuit arrangement for delaying a useful signal which is stored in the form of time-discrete signal samples in a row of storage devices at time intervals which are determined by a clock signal and is read therefrom after expiration of a selectable delay time. Each storage device is connectable, via a respective input circuit to a useful signal input and, via a respective output circuit, to a useful signal output. The the input circuit of a storage device being activatable, together with the output circuit of the next storage device in the row, by a respective activation device, which includes a shift register device formed by a chain of bistable trigger circuits in which the output of each of the trigger circuits is connected to the input of the next trigger circuit in the chain, each activation device including one of the trigger circuits and all trigger circuits being switched by the clock signal, and also comprising a command device which applies a (first) start pulse to the first trigger circuit in the shift register device at a first instant and which enables the shift register device to propagate the start pulse through the chain of trigger circuits in conformity with the clock signal and which interrupts the propagation of the (first) start pulse at a second instant and at the same time applies a next start pulse to the first trigger circuit in the shift register device and enables the shift register device again to propagate said next start pulse, the time interval between the first instance (t1) and the second instant (t10) amounting to a selectable, integer multiple of periods of the clock signal, the number (n) of storage devices or trigger circuits corresponding at least to said multiple (n) of the periods of the clock signal. This circuit arrangement can be simply adapted to a plurality of different desired delay time values, during operation.
REFERENCES:
patent: 4443765 (1984-04-01), Findeisen et al.
patent: 5016263 (1991-05-01), Kitagawa et al.
patent: 5287025 (1994-02-01), Nishimichi
Gathman Laurie E.
Nelms David C.
Phan Trong
U.S. Philips Corporation
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