Circuit arrangement for decoding digital signals

Pulse or digital communications – Spread spectrum – Direct sequence

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375116, 375 94, 375 95, H04L 700

Patent

active

042427550

ABSTRACT:
A demodulator for binary messages of the diphase type comprises a sampling circuit controlled by a local clock whose cycle is approximately 1
.sup.th of the bit length of the incoming signals (with n=8 in a specific instance), this circuit deriving (n-2) samples from each message bit which are then analyzed in a programmed memory to determine whether the bit being sampled has one of six acceptable configurations, namely a bit of logical value "0" or "1" in either a normal, a leading or a lagging position with reference to a decoding interval T equaling n clock cycles. If a different configuration is detected, an error signal is generated. The decoding interval is measured by a counter, stepped by the local clock, which is adjusted by recalibrating commands from the programmed memory to shorten or lengthen the next decoding interval when a bit is found to lead or lag by a full clock cycle, thereby restoring the normal relative time position of the message bits and the decoding interval. A validation signal emitted by the bit analyzer in the presence of an acceptable configuration enables the generation of a synchronization pulse at a predetermined time in the decoding interval to mark the instant at which the received message bit can be correctly read either in a reconstituted bit sequence or in the original binary pulse train delayed by one interval T of n clock cycles.

REFERENCES:
patent: 3335224 (1967-08-01), Meslener
patent: 3390233 (1968-06-01), Brothman
patent: 3396369 (1968-08-01), Brothman
patent: 3757226 (1973-09-01), Stover
patent: 3908084 (1975-09-01), Wiley
patent: 3920900 (1975-11-01), Fineman
patent: 3961138 (1976-01-01), Fellinger
patent: 4012598 (1977-03-01), Wiley
patent: 4035601 (1977-07-01), Isaacs
patent: 4130724 (1978-12-01), Bousmar

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