Circuit arrangement for decimal arithmetic

Details Circuit arrangement for decimal arithmetic Circuit arrangement for decimal arithmetic

1990-06-28

1992-02-04

Malzahn, David H.

Boots, shoes, and leggings

364768, G06F 750

Patent

active

050864068

ABSTRACT:
A circuit for performing decimal subtraction at high speed has an execution time which is independent of the existence of a borrow condition. The subtraction circuit is particularly suited for use in microcoded computer circuits.

REFERENCES:
patent: 4811272 (1989-03-01), Wolrich et al.
patent: 4849921 (1989-07-01), Yasumoto et al.
patent: 4866656 (1989-09-01), Hwang
Chu, "Organization of a Decimal Arithmetic Unit," Computer Organization and Microprogramming, Prentice-Hall, Inc., 1972, pp. 230-243.

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