Circuit arrangement for current limiting

Electricity: electrical systems and devices – Safety and protection of systems and devices – Impedance insertion

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Details

361101, 307131, H02H 900

Patent

active

057935890

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to a circuit arrangement for current limiting which is arranged between a supply voltage source and a storage capacitor and contains, in a series path, the source-drain path of a field-effect transistor and a current sensor connected in series with the source-drain path, the gate of the field-effect transistor being connected via a resistor to a turn-on potential, which switches the field-effect transistor on, and via the emitter-collector path of a transistor to a blocking potential, which switches the field-effect transistor into the off state, the emitter of the transistor being connected to one end of the current sensor and the base of the transistor being connected via a resistor to the other end of the current sensor, with the result that the emitter-collector path of the transistor has a high impedance in the event of voltage drops across the current sensor below a predetermined threshold voltage, and, in the event of voltage drops across the current sensor above the predetermined threshold voltage, the collector of the transistor emits a potential which controls the field-effect transistor in the sense of current limiting.
2. Description of the Related Art
A circuit arrangement of this type has already been disclosed in the German Patent Document DE-35 35 864-A1. The drain-source path of a field-effect transistor is arranged in the series path of the known circuit arrangement. A measuring resistor is connected as a current sensor in series with the drain-source path of the field-effect transistor. The voltage drop across the measuring resistor controls a bipolar transistor. The gate of the field-effect transistor is connected both via a resistor to a turn-on potential, which switches the field-effect transistor on, and via the emitter-collector path of the bipolar transistor to a blocking potential, which switches the field-effect transistor off. With the aid of the field-effect transistor, a charging current, which flows after the power supply voltage has been turned on and which charges a capacitor, is limited to a predetermined value.
In the case of assemblies having a capacitor connected in parallel with the input or output, high charging currents occur in the event of live plugging or when a voltage is connected to the capacitor. This is the case, in particular, when assemblies which have buffer capacitors for the power supply are plugged during operation onto printed circuit boards with voltage-carrying bus lines of low impedance. Such buffer capacitors may be present, in particular, at the input of switched-mode power supply devices or at outputs of power surely devices which are connected in parallel with one another for the purpose of the redundant feeding of loads.
With the aid of a circuit arrangement for current limiting having a field-effect transistor and a current measuring resistor, it is possible to limit the charging current in the event of plugging or the application of the operating voltage, and also during operation. However, this limiting has a typical reaction time of a few microseconds. If assemblies are withdrawn during operation, then brief recharging current pulses, which reach a multiple of the steady-state limit value, can occur due to bouncing of the plug contacts. This can bring about interference particularly in telecommunications arrangements situated on adjacent assemblies.


SUMMARY OF THE INVENTION

Considerations within the context of the present invention have revealed that the abovementioned difficulties do not arise when, instead of limiting the current itself, the very rate of rise of the current is limited.
An object of the invention, therefore, is to provide a circuit arrangement in such a way that it effectively limits not only the current, but also the rate of rise of the current.
According to the invention, the circuit arrangement is for current limiting, which is arranged between a supply voltage source and a storage capacitor and contains, in a series path, the source

REFERENCES:
patent: 4438473 (1984-03-01), Cawley et al.
patent: 4939776 (1990-07-01), Bender
patent: 5347169 (1994-09-01), Preslar et al.
patent: 5539820 (1996-07-01), Pistilli

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