Circuit arrangement for correction of data

Details Circuit arrangement for correction of data Circuit arrangement for correction of data

1979-11-19

1982-02-23

Smith, Jerry

Excavating

371 44, G06F 1112

Patent

active

043172024

ABSTRACT:
Circuit arrangement for the correction of data transmitted over a communication channel incorporates a shift register and a parity stage at the transmission side of the channel for generating parity bits, and similar equipment located at the reception side of the channel for generating similar parity bits. The parity bits are compared to provide syndrome signals, and the syndrome signals are stored in a syndrome shift register having a plurality of taps. A majority stage is effective to make corrections in the transmitted data when a majority of the syndrome signals at the taps of the syndrome register indicate an error condition. The taps of the shift registers employed for the parity generation and the taps of the syndrome shift register are spaced at unequal intervals. Four, six or eight taps are employed.

REFERENCES:
patent: 3402393 (1968-09-01), Massey
patent: 3571795 (1971-03-01), Tong
patent: 3605090 (1971-09-01), Burton
patent: 3718905 (1973-02-01), Tong
patent: 4193062 (1980-03-01), En
"Convolutional Coding for Channels with Memory", IEEE Trans. on Information Theory, vol. IT-14, No. 5, 9-1968, pp. 618-626.

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