Communications: electrical – Digital comparator systems
Patent
1975-04-11
1976-02-10
Atkinson, Charles E.
Communications: electrical
Digital comparator systems
H04L 700
Patent
active
039380866
ABSTRACT:
A receiver of n-bit data words, each consisting of k information bits and (n-1) redundancy bits, comprises three error detectors receiving the incoming bit stream in parallel with one another and with a shift register of a transfer circuit, the three error detectors being triggered by timing pulses fed to them in staggered relationship from a clock circuit extracting synchronizing signals from the bit stream. In normal operation, the middle detector generates a recurrent no-error output signal which has no effect upon the cadence of the timing pulses. If either of the two other detectors emits such a no-error output signal in response to a forward or a backward slip by a predetermined number of bits h, the clock circuit is reset to compensate for the slip. The emission of an output signal from any error detector causes the readout of the received bits from the shift register in the transfer circuit.
REFERENCES:
patent: 3466601 (1969-09-01), Tong
patent: 3550082 (1970-12-01), Tong
patent: 3571794 (1971-03-01), Tong
patent: 3761891 (1973-09-01), Markwitz
patent: 3873773 (1975-03-01), Guy, Jr.
Atkinson Charles E.
Dubno Herbert
Ross Karl F.
Societa Italiana Telecomunicazioni Siemens S.p.A.
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