Circuit arrangement for converting a serial data signal into a p

Details Circuit arrangement for converting a serial data signal into a p Circuit arrangement for converting a serial data signal into a p

1995-08-08

1998-06-30

Gaffin, Jeffrey A.

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

341101, H03M 900

Patent

active

057740798

ABSTRACT:
A serial/parallel converter includes a shift register arrangement (12', 12" to 12.sup.n) and an output register arrangement (13', 13" to 13.sup.n), each of which includes n storage devices (12', 12" to 12.sup.n ; 13', 13" to 13.sup.n). Each of the storage devices (13', 13" to 13.sup.n) of at least the output register arrangement includes two data inputs (DP, DS), a selection input (S) for selecting a data input, a clock input (CLK) as well as a data output (Q). The individual clock inputs (CLK) of the storage devices (13', 13" to 13.sup.n) receive a serial data signal and the selection inputs (S) receive a frequency-divided clock signal. Second data inputs (DS) of the storage devices (13', 13" to 13.sup.n) are connected to the data outputs (Q) of the shift register arrangement (12', 12" to 12.sup.n), the first data input (DP) of said storage devices being connected to the own data output (Q). The data signal can be derived in parallel from the data outputs (Q) of the storage devices (13', 13" to 13.sup.n).

REFERENCES:
patent: 3395400 (1968-07-01), De Witt et al.
patent: 3763480 (1973-10-01), Weimer
patent: 5128673 (1992-07-01), Tamamura et al.
patent: 5223833 (1993-06-01), Akata
patent: 5337050 (1994-08-01), Sugawara
patent: 5548285 (1996-08-01), Ford et al.

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