Circuit arrangement for conversion TTL logic signals to ECL logi

Details Circuit arrangement for conversion TTL logic signals to ECL logi Circuit arrangement for conversion TTL logic signals to ECL logi

1983-05-05

1986-08-19

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 307264, H03K 19092, H03K 19086, H03K 19003

Patent

active

046071776

ABSTRACT:
A circuit arrangement for level conversion of TTL-logic levels to ECL-logic levels with at least one emitter-coupled current switch having an input addressable by TTL-logic levels and an output from which ECL-logic levels can be taken off, including a first current switch formed of two emitter-coupled npn-transistors (and a second current switch formed of two emitter-coupled pnp-transistors, one of the transistors of the second current switch being arranged as input stage for the first current switch, the second current switch having a switching threshold higher than that of the first current switch.

REFERENCES:
patent: 3558914 (1971-01-01), Schmidt
patent: 3688127 (1972-08-01), Potter et al.
patent: 3787737 (1974-01-01), Mukai
patent: 3860830 (1975-01-01), Sugiura et al.
patent: 4356409 (1982-10-01), Masuda et al.
patent: 4357548 (1982-11-01), Preslar
patent: 4533842 (1985-08-01), Yang et al.
The Integrated Circuits Catalog for Design Engineers, First Edition, Texas Instruments, 1971, pp. 4-73 to 4-48.
Motorola MECL Integrated Circuits, prepared by Technical Information Center, 1978, pp. 3-19.

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