Circuit arrangement for controlling threshold voltages in CMOS c

Details Circuit arrangement for controlling threshold voltages in CMOS c Circuit arrangement for controlling threshold voltages in CMOS c

1984-10-05

1987-06-02

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307442, 307200B, 307491, 307308, 307304, 307496, H03L 100, H03K 19003, H03K 19007, G05F 500

Patent

active

046706704

ABSTRACT:
The threshold voltage of a CMOS circuit is stabilized by a feedback loop which responds to variations in threshold voltage of a reference FET to provide a backbias voltage to readjust the threshold voltage of a second FET. The circuit is particularly useful to overcome threshold variations due to .gamma.-radiation.

REFERENCES:
patent: 4435652 (1984-03-01), Stevens
patent: 4471290 (1984-09-01), Yamaguchi
patent: 4549096 (1985-10-01), Hoffmann
Debar, "Dynamic Substrate Bias to Achieve Radiation Hardening"; IBM-TDB; vol. 25, No. 11A, pp. 5829-5830; 4/1983.
Harroun, "Substrate Bias Voltage Control"; IBM-TDB; vol. 22, No. 7, pp. 2691-2692; 12/1979.
Hoffman, "Self-Adjusting Bias Current Generator for IC Amplifier"; IBM-TDB; vol. 23, No. 7B, pp. 3330-3331; 12/1980.
R. T. Davis, M. H. Woods, W. E. Will, P. R. Measel, "High-Performance MOS Resists Radiation", Electronics, Nov. 17, 1982, pp. 137-139.

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