Circuit arrangement for controlling a high side CMOS...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver

Reexamination Certificate

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Details

C327S109000, C327S390000

Reexamination Certificate

active

08004318

ABSTRACT:
The present invention relates to a circuit arrangement, which is used for controlling a high side CMOS transistor (M1) in a high voltage deep sub micron process. To provide a circuit arrangement for switching a high side CMOS transistor (M1) in a circuit having a very thin gate oxide, produced by a deep sub micron process, a circuit arrangement is proposed for controlling a high side CMOS transistor (M1), wherein the high side CMOS transistor (M1) is coupled between a high side voltage potential (Vbat) and a control output (OUT) for switching an external device, the high side CMOS transistor (M1) is controlled at its gate by a reference potential (Vbat-Vref), which is provided by a high side voltage reference (11) having a capacitor (C1), which is charged for switching on and discharged for switching off the high side CMOS transistor (M1).

REFERENCES:
patent: 4266149 (1981-05-01), Yoshida
patent: 4965696 (1990-10-01), Kumpfmueller et al.
patent: 5120992 (1992-06-01), Miller et al.
patent: 5317206 (1994-05-01), Hanibuchi et al.
patent: 5587895 (1996-12-01), Harkins
patent: 5633600 (1997-05-01), Ohnishi
patent: 5721485 (1998-02-01), Hsu et al.
patent: 6433592 (2002-08-01), Ehben
patent: 6465996 (2002-10-01), Nagata et al.
patent: 7098633 (2006-08-01), Brokaw et al.
patent: 7388422 (2008-06-01), Khan et al.
patent: 2002/0175719 (2002-11-01), Cohen
patent: 2005/0184759 (2005-08-01), Tsukada
patent: 1469603 (2004-10-01), None
patent: 57-017162 (1982-01-01), None
patent: 99/59249 (1999-11-01), None
Ong, A.K., et al; “A Method for Reducing the Variation in on Resistance of a MOS Sampling Switch”; Circuits and Systems, 2000; 2000 IEEE International Symposium on May 28-31, 2000, Piscataway, NY, USA; IEEE vol. 5; pp. 437-440; XP010504227; ISBN: 0-7803-5482-6.

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